Stephen Bijansky

According to our database1, Stephen Bijansky authored at least 4 papers between 2004 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
TuneLogic: Post-silicon tuning of dual-Vdd designs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Adaptive SRAM memory for low power and high yield.
Proceedings of the 26th International Conference on Computer Design, 2008

TuneFPGA: post-silicon tuning of dual-Vdd FPGAs.
Proceedings of the 45th Design Automation Conference, 2008

2004
Defect tolerant probabilistic design paradigm for nanotechnologies.
Proceedings of the 41th Design Automation Conference, 2004


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