Stephen Bates
Orcid: 0000-0002-3273-8179
According to our database1,
Stephen Bates
authored at least 57 papers
between 1996 and 2024.
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Bibliography
2024
CoRR, 2024
Proceedings of the Forty-first International Conference on Machine Learning, 2024
Proceedings of the Twelfth International Conference on Learning Representations, 2024
On Counterfactual Metrics for Social Welfare: Incentives, Ranking, and Information Asymmetry.
Proceedings of the International Conference on Artificial Intelligence and Statistics, 2024
Proceedings of the International Conference on Artificial Intelligence and Statistics, 2024
2023
J. Mach. Learn. Res., 2023
Operationalizing Counterfactual Metrics: Incentives, Ranking, and Information Asymmetry.
CoRR, 2023
Proceedings of the 24th ACM Conference on Economics and Computation, 2023
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the Conformal and Probabilistic Prediction with Applications, 2023
Proceedings of the Conformal and Probabilistic Prediction with Applications, 2023
2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
Image-to-Image Regression with Distribution-Free Uncertainty Quantification and Applications in Imaging.
Proceedings of the International Conference on Machine Learning, 2022
2021
CoRR, 2021
A Gentle Introduction to Conformal Prediction and Distribution-Free Uncertainty Quantification.
CoRR, 2021
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Proceedings of the 9th International Conference on Learning Representations, 2021
2020
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020
2015
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
2010
Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2009
A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
2008
Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
A Low-Cost Serial Decoder Architecture for Low-Density Parity-Check Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Integr., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and Decoder.
IEEE J. Solid State Circuits, 2007
Proceedings of the Managing Traffic Performance in Converged Networks, 2007
2006
Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006
2005
Construction of low-density parity-check convolutional codes through progressive edge-growth.
IEEE Commun. Lett., 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Low-density parity-check convolutional codes applied to packet based communication systems.
Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005
2004
Proceedings of the Telecommunications and Networking, 2004
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004
VLSI Issues for the Implementation of 10GBASE-T Ethernet.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
Proceedings of the Ad-Hoc, Mobile, and Wireless Networks: Third International Conference, 2004
2000
IEEE Trans. Signal Process., 2000
1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
1996
Is VBR Video Non-Stationary or Self-Similar? Implications for ATM Traffic Characterisation.
Proceedings of the Modelling and Simulation, 1996