Stephanie Youssef
According to our database1,
Stephanie Youssef
authored at least 3 papers
between 2010 and 2011.
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Bibliography
2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
A seamless representation for coupling transistor sizing with nanometric CMOS layout generation.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Automatic stress effects computation based on a layout generation tool for analog IC.
Proceedings of the 2010 IEEE International Behavioral Modeling and Simulation Conference, 2010