Stephan Niel

According to our database1, Stephan Niel authored at least 11 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
40nm SONOS Embedded Select in Trench Memory.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022
Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Schmitt trigger to benchmark the performance of a new zero-cost transistor.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Hot Electron Source Side Injection Comprehension in 40nm eSTM™.
Proceedings of the IEEE International Memory Workshop, 2021

Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020
AC stress reliability study of a new high voltage transistor for logic memory circuits.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2018
Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2015
Dynamic current reduction of CMOS digital circuits through design and process optimization.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Layout optimizations to decrease internal power and area in digital CMOS standard cells.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015

2014
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014


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