Stephan Menzel
Orcid: 0000-0002-4258-2673
According to our database1,
Stephan Menzel
authored at least 64 papers
between 2010 and 2024.
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Bibliography
2024
Improved Arithmetic Performance by Combining Stateful and Non-Stateful Logic in Resistive Random Access Memory 1T-1R Crossbars.
Adv. Intell. Syst., March, 2024
Neuromorph. Comput. Eng., 2024
Employing Vector Field Techniques on the Analysis of Memristor Cellular Nonlinear Networks Cell Dynamics.
CoRR, 2024
Synaptogen: A cross-domain generative device model for large-scale neuromorphic circuit design.
CoRR, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Memory Workshop, 2024
2023
Neuromorph. Comput. Eng., December, 2023
A Physical Description of the Variability in Single-ReRAM Devices and Hardware-Based Neuronal Networks.
Adv. Intell. Syst., November, 2023
Neuromorph. Comput. Eng., June, 2023
it Inf. Technol., May, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
Proceedings of the 19th International Conference on Synthesis, 2023
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Exploration of Bistable Oscillatory Dynamics in a Memristor from Forschungszentrum Jülich.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023
Design and Analysis of Isolated Voltage-Mode Memristor Cellular Nonlinear Network Cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Memory Workshop, 2023
Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing.
Proceedings of the IEEE International Memory Workshop, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
2022
Toward Simplified Physics-Based Memristor Modeling of Valence Change Mechanism Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Neuromorph. Comput. Eng., 2022
Neuromorph. Comput. Eng., 2022
MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory.
ACM J. Emerg. Technol. Comput. Syst., 2022
A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022
Proceedings of the IEEE International Test Conference in Asia, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Experimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Analysis of VMM Operations on 1S1R Crossbar Arrays and the Influence of Wire Resistances.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022
2021
J. Electron. Test., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Machine Learning Model for Predicting Fetal Hemoglobin Levels in Sickle Cell Disease Patients.
Proceedings of Sixth International Congress on Information and Communication Technology, 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
2020
Variability-Aware Modeling of Filamentary Oxide-Based Bipolar Resistive Switching Cells Using SPICE Level Compact Models.
IEEE Trans. Circuits Syst., 2020
In-Memory Binary Vector-Matrix Multiplication Based on Complementary Resistive Switches.
Adv. Intell. Syst., 2020
Proceedings of the European Conference on Circuit Theory and Design, 2020
2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
ACM J. Emerg. Technol. Comput. Syst., 2018
The influence of interfacial (sub)oxide layers on the properties of pristine resistive switching devices.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
Atomistic Investigation of the Schottky Contact Conductance Limits at SrTiO3 based Resistive Switching Devices.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Thermal effects on the I-V characteristics of filamentary VCM based ReRAM-cells using a nanometer-sized heater.
Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017
Kinetic Monte Carlo modeling of the charge transport in a HfO2-based ReRAM with a rough anode.
Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017
2016
Efficient implementation of multiplexer and priority multiplexer using 1S1R ReRAM crossbar arrays.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Energy dissipation during pulsed switching of strontium-titanate based resistive switching memory devices.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Controllability of multi-level states in memristive device models using a transistor as current compliance during SET operation.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
2014
Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Simulation and comparison of two sequential logic-in-memory approaches using a dynamic electrochemical metallization cell model.
Microelectron. J., 2014
Simulation of TaOx-based complementary resistive switches by a physics-based memristive model.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2010