Stephan Kassenetter

According to our database, Stephan Kassenetter authored at least 3 papers between 2012 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS.

Mihail Jefremow, Thomas Kern, Wolf Allers, Christian Peters, Jan Otterstedt, Othmane Bahlous, Karl Hofmann, Robert Allinger, Stephan Kassenetter, Doris Schmitt-Landsiedel

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 65nm 4MB embedded flash macro for automotive achieving a read throughput of 5.7GB/s and a write throughput of 1.4MB/s.

Mihail Jefremow, Thomas Kern, Ulrich Backhausen, J. Elbs, B. Rousseau, Christoph Roll, L. Castro, T. Roehr, E. Paparisto, K. Herfurth, R. Bartenschlager, Stefanie Thierold, R. Renardy, Stephan Kassenetter, N. Lawal, M. Strasser, W. Trottmann, Doris Schmitt-Landsiedel

Proceedings of the ESSCIRC 2013, 2013

2012

Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive.

Mihail Jefremow, Thomas Kern, Ulrich Backhausen, Christian Peters, Christoph Parzinger, Christoph Roll, Stephan Kassenetter, Stefanie Thierold, Doris Schmitt-Landsiedel

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012