Stephan Henzler
According to our database1,
Stephan Henzler
authored at least 20 papers
between 2003 and 2016.
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Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2016
A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2009
Adaptive circuit block model for power supply noise analysis of low power system-on-chip.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion.
IEEE J. Solid State Circuits, 2008
90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions.
IEEE J. Solid State Circuits, 2007
In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations.
IEEE J. Solid State Circuits, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead.
IEEE J. Solid State Circuits, 2006
A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits.
Proceedings of the Second Conference on Computing Frontiers, 2005
2004
Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.
Proceedings of the Integrated Circuit and System Design, 2004
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.
Proceedings of the Integrated Circuit and System Design, 2004
2003
Proceedings of the VLSI-SOC: From Systems to Chips, 2003
Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes.
Proceedings of the IFIP VLSI-SoC 2003, 2003