Stephan Held

Orcid: 0000-0003-2188-1559

Affiliations:
  • University of Bonn, Germany


According to our database1, Stephan Held authored at least 29 papers between 2003 and 2024.

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Bibliography

2024
Constrained Local Search for Last-Mile Routing.
Transp. Sci., 2024

Vehicle routing with time-dependent travel times: Theory, practice, and benchmarks.
Discret. Optim., 2024

2023
Global Interconnect Optimization.
ACM Trans. Design Autom. Electr. Syst., September, 2023

Approximating the discrete time-cost tradeoff problem with bounded depth.
Math. Program., February, 2023

Tighter Approximation for the Uniform Cost-Distance Steiner Tree Problem.
Proceedings of the Approximation, 2023

2022
Further Improvements on Approximating the Uniform Cost-Distance Steiner Tree Problem.
CoRR, 2022

Challenges and Approaches in VLSI Routing.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2020
An Improved Approximation Algorithm for the Uniform Cost-Distance Steiner Tree Problem.
Proceedings of the Approximation and Online Algorithms - 18th International Workshop, 2020

2019
Vehicle routing with subtours.
Discret. Optim., 2019

2018
An Approximation Algorithm for Threshold Voltage Optimization.
ACM Trans. Design Autom. Electr. Syst., 2018

Global Routing With Timing Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Provably Fast and Near-Optimum Gate Sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two.
ACM Trans. Algorithms, 2018

Exact algorithms for delay-bounded steiner arborescences.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Two-level rectilinear Steiner trees.
Comput. Geom., 2017

Fast Prefix Adders for Non-uniform Input Arrival Times.
Algorithmica, 2017

2015
Global Routing with Inherent Static Timing Constraints.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Local search algorithms for timing-driven placement under arbitrary delay models.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
A fast algorithm for rectilinear steiner trees with length restrictions on obstacles.
Proceedings of the International Symposium on Physical Design, 2014

Post-Routing Latch Optimization for Timing Closure.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Shallow-Light Steiner Arborescences with Vertex Delays.
Proceedings of the Integer Programming and Combinatorial Optimization, 2013

2012
Maximum-weight stable sets and safe lower bounds for graph coloring.
Math. Program. Comput., 2012

2011
Combinatorial Optimization in VLSI Design.
Proceedings of the Combinatorial Optimization - Methods and Applications, 2011

Safe Lower Bounds for Graph Coloring.
Proceedings of the Integer Programming and Combinatoral Optimization, 2011

2010
The repeater tree construction problem.
Inf. Process. Lett., 2010

2009
Fast buffering for optimizing worst slack and resource consumption in repeater trees.
Proceedings of the 2009 International Symposium on Physical Design, 2009

Gate sizing for large cell-based designs.
Proceedings of the Design, Automation and Test in Europe, 2009

2006
Efficient generation of short and fast repeater tree topologies.
Proceedings of the 2006 International Symposium on Physical Design, 2006

2003
Clock Scheduling and Clocktree Construction for High Performance ASICS.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003


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