Stephan Eggersglüß

According to our database, Stephan Eggersglüß authored at least 56 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

The Future of Design for Test and Silicon Lifecycle Management.

Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer

IEEE Des. Test, August, 2024

A Cell-aware Transistor State Stress Model and its Application for Quality Measurement.

Stephan Eggersglüß, Andreas Glowatz

Proceedings of the IEEE International Test Conference, 2024

2023

A New Static Compaction of Deterministic Test Sets.

Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

2021

On Reduction of Deterministic Test Pattern Sets.

Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer

Proceedings of the IEEE International Test Conference, 2021

2019

Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements.

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler

Proceedings of the IEEE Latin American Test Symposium, 2019

IEEE European Test Symposium (ETS).

Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena-Ioana Vatajelu

Proceedings of the IEEE International Test Conference, 2019

Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques.

Stephan Eggersglüß

Proceedings of the IEEE International Test Conference, 2019

Machine Learning-based Prediction of Test Power.

Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing.

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Approximation-aware testing for approximate circuits.

Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements.

Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler

Proceedings of the 2017 IEEE Symposium Series on Computational Intelligence, 2017

Foreword.

Maria K. Michael, Rolf Drechsler, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken

Proceedings of the 22nd IEEE European Test Symposium, 2017

Reconfigurable TAP controllers with embedded compression for large test data volume.

Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Machine learning based test pattern analysis for localizing critical power activity areas.

Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression.

Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Identification of Efficient Clustering Techniques for Test Power Activity on the Layout.

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets.

Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Exploring superior structural materials using multi-objective optimization and formal techniques.

Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers.

Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler

Proceedings of the 21th IEEE European Test Symposium, 2016

SAT-based post-processing for regional capture power reduction in at-speed scan test generation.

Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen

Proceedings of the 21th IEEE European Test Symposium, 2016

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test.

Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Compact test set generation for test compression-based designs.

Stephan Eggersglüß

Proceedings of the 20th IEEE European Test Symposium, 2015

2014

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques.

Stephan Eggersglüß, Rolf Drechsler

it Inf. Technol., 2014

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets.

Stephan Eggersglüß

J. Electron. Test., 2014

Automated formal verification of X propagation with respect to testability issues.

Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß

Proceedings of the 9th International Design and Test Symposium, 2014

Optimization-based multiple target test generation for highly compacted test sets.

Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler

Proceedings of the 19th IEEE European Test Symposium, 2014

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization.

Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2013

PASSAT 2.0: A multi-functional SAT-based testing framework.

Rolf Drechsler, Melanie Diepenbeck, Stephan Eggersglüß, Robert Wille

Proceedings of the 14th Latin American Test Workshop, 2013

Improved SAT-based ATPG: more constraints, better compaction.

Stephan Eggersglüß, Robert Wille, Rolf Drechsler

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill.

Stephan Eggersglüß

Proceedings of the 22nd Asian Test Symposium, 2013

2012

A Highly Fault-Efficient SAT-Based ATPG Flow.

Stephan Eggersglüß, Rolf Drechsler

IEEE Des. Test Comput., 2012

A new SAT-based ATPG for generating highly compacted test sets.

Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization.

Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty

Proceedings of the 21st IEEE Asian Test Symposium, 2012

High Quality Test Pattern Generation and Boolean Satisfiability.

Stephan Eggersglüß, Rolf Drechsler

Springer, ISBN: 978-1-4419-9975-7, 2012

2011

Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application.

Stephan Eggersglüß, Rolf Drechsler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization.

Stephan Eggersglüß, Rolf Drechsler

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Robust algorithms for high quality test pattern generation using Boolean satisfiability.

Stephan Eggersglüß

PhD thesis, 2010

Incremental Solving Techniques for SAT-based ATPG.

Daniel Tille, Stephan Eggersglüß, Rolf Drechsler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics.

Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler

J. Electron. Test., 2010

Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation.

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Robuste Erfüllbarkeitsalgorithmen zur Generierung hochwertiger Testmuster für digitale Schaltungen.

Stephan Eggersglüß

Proceedings of the Ausgezeichnete Informatikdissertationen 2010, 2010

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs.

Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler

Proceedings of the 15th European Test Symposium, 2010

2009

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation).

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille

it Inf. Technol., 2009

Timing Arc based logic analysis for false noise reduction.

Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques.

Stephan Eggersglüß, Rolf Drechsler

Proceedings of the 14th IEEE European Test Symposium, 2009

Speeding up SAT-Based ATPG Using Dynamic Clause Activation.

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Test Pattern Generation using Boolean Proof Engines.

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille

Springer, ISBN: 978-90-481-2359-9, 2009

2008

On Acceleration of SAT-Based ATPG for Industrial Designs.

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults.

Stephan Eggersglüß, Rolf Drechsler

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

SAT-based Automatic Test Pattern Generation.

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille

Proceedings of the Evolutionary Test Generation, 24.08. - 29.08.2008, 2008

2007

SWORD: A SAT like Prover Using Word Level Information.

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler

Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Formal Verification on the Word Level using SAT-like Proof Techniques.

Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Experimental Studies on SAT-Based ATPG for Gate Delay Faults.

Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

SAT-based ATPG for Path Delay Faults in Sequential Circuits.

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Improving Test Pattern Compactness in SAT-based ATPG.

Stephan Eggersglüß, Rolf Drechsler

Proceedings of the 16th Asian Test Symposium, 2007