Steffen Buch

Orcid: 0009-0000-0778-8126

According to our database1, Steffen Buch authored at least 6 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2023
Error Detecting and Correcting Codes for DRAM Functional Safety.
Proceedings of the International Symposium on Memory Systems, 2023

2007
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions.
IEEE J. Solid State Circuits, 2007

2006
Low power synthesizable register files for processor and IP cores.
Integr., 2006

2004
An instruction set for the efficient implementation of the CORDIC algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002
Low power register file architecture for application specific DSPs.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Testability of path history memories with register-exchange architecture used in Viterbi-decoders.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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