Stefanos Sidiropoulos

According to our database, Stefanos Sidiropoulos authored at least 13 papers between 1991 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.

Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2013

A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications.

Aida Varzaghani, Athos Kasapi, Dimitri Loizos, Song-Hee Paik, Shwetabh Verma, Sotirios Zogopoulos, Stefanos Sidiropoulos

IEEE J. Solid State Circuits, 2013

A 10.3GS/s 6b flash ADC for 10G Ethernet applications.

Shwetabh Verma, Athos Kasapi, Li-min Lee, Dean Liu, Dimitri Loizos, Song-Hee Paik, Aida Varzaghani, Sotirios Zogopoulos, Stefanos Sidiropoulos

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2006

An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOS.

Shahriar Rabii, Nikhil Acharya, Pak Chau, Joseph Dao, Arnold Feldman, Haw-Jyh Liaw, Dean Liu, Marc Loinaz, Manuel Luschas, Azmeer Salleh, Siddharth Sheth, Stefanos Sidiropoulos, Donald Stark, Shwetabh Verma

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Improving CDR Performance via Estimation.

Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003

A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs.

Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos

IEEE J. Solid State Circuits, 2003

A Framework for Designing Reusable Analog Circuits.

Dean Liu, Stefanos Sidiropoulos, Mark Horowitz

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2000

A variable-frequency parallel I/O interface with adaptive power-supply regulation.

Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos, Mark A. Horowitz

IEEE J. Solid State Circuits, 2000

1998

High-speed electrical signaling: overview and limitations.

Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos

IEEE Micro, 1998

1997

A semidigital dual delay-locked loop.

Stefanos Sidiropoulos, Mark A. Horowitz

IEEE J. Solid State Circuits, 1997

A 700-Mb/s/pin CMOS signaling interface using current integrating receivers.

Stefanos Sidiropoulos, Mark Horowitz

IEEE J. Solid State Circuits, 1997

1996

A speed, power, and supply noise evaluation of ECL driver circuits.

Norman P. Jouppi, Stefanos Sidiropoulos, Suresh Menon

IEEE J. Solid State Circuits, 1996

1991

Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip.

Manolis Katevenis, Stefanos Sidiropoulos, Costas Courcoubetis

IEEE J. Sel. Areas Commun., 1991