Stefanos Kaxiras

Erik Hagersten

Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014

Power-Efficient Computer Architectures: Recent Advances

[BibT_eX]

[DOI]

Magnus Själander

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01745-2, 2014

Managing power constraints in a single-core scenario through power tokens.

[BibT_eX]

[DOI]

J. Supercomput., 2014

A tunable cache for approximate computing.

[BibT_eX]

[DOI]

Magnus Själander

Nina Shariati Nilsson

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Fix the code. Don't tweak the hardware: A new compiler approach to Voltage-Frequency scaling.

[BibT_eX]

[DOI]

Alexandra Jimborean

Konstantinos Koukos

David Black-Schaffer

Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

2013

Efficient inter-core power and thermal balancing for multicore processors.

[BibT_eX]

[DOI]

Computing, 2013

Introducing DVFS-Management in a Full-System Simulator.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 21st International Symposium on Modelling, 2013

A new perspective for efficient virtual-cache coherence.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Towards more efficient execution: a decoupled access-execute approach.

[BibT_eX]

[DOI]

Konstantinos Koukos

David Black-Schaffer

Proceedings of the International Conference on Supercomputing, 2013

2012

Efficient, snoopless, System-on-Chip coherence.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International SOC Conference, 2012

A framework for efficient cache resizing.

[BibT_eX]

[DOI]

Chrysovalantis Datsios

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Power-Sleuth: A Tool for Investigating Your Program's Power Behavior.

[BibT_eX]

[DOI]

Andreas Sembrant

Proceedings of the 20th IEEE International Symposium on Modeling, 2012

Embedded reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Compilers, 2012

Complexity-effective multicore coherence.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

Leakage-efficient design of value predictors through state and non-state preserving techniques.

[BibT_eX]

[DOI]

J. Supercomput., 2011

Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads.

[BibT_eX]

[DOI]

Juan M. Cebrian

Juan L. Aragón

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Poster: DVFS management in real-processors.

[BibT_eX]

[DOI]

Konstantinos Efstathiou

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Green governors: A framework for Continuously Adaptive DVFS.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Token3D: Reducing Temperature in 3D Die-Stacked CMPs through Cycle-Level Power Control Mechanisms.

[BibT_eX]

[DOI]

Juan M. Cebrian

Juan L. Aragón

Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

Multicore Cache Simulations Using Heterogeneous Computing on General Purpose and Graphics Processors.

[BibT_eX]

[DOI]

Nikolaos Strikos

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

SARC Coherence: Scaling Directory Cache Coherence in Performance and Power.

[BibT_eX]

[DOI]

IEEE Micro, 2010

Teaching Introduction to Computing Through a Project-Based Collaborative Learning Approach.

[BibT_eX]

[DOI]

Nikolaos M. Avouris

Odysseas G. Koufopavlou

Kyriakos N. Sgarbas

Polyxeni Stathopoulou

Proceedings of the 14th Panhellenic Conference on Informatics, 2010

Interval-based models for run-time DVFS orchestration in superscalar processors.

[BibT_eX]

[DOI]

Proceedings of the 7th Conference on Computing Frontiers, 2010

Where replacement algorithms fail: a thorough analysis.

[BibT_eX]

[DOI]

Proceedings of the 7th Conference on Computing Frontiers, 2010

MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance.

[BibT_eX]

[DOI]

Georgia Psychou

Juan Manuel Cebrian Gonzalez

Juan L. Aragón

Proceedings of the Architecture of Computing Systems, 2010

2009

Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2009

Instruction-based reuse-distance prediction for effective cache management.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Efficient microarchitecture policies for accurately adapting to power constraints.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Instruction Precomputation for Fault Detection.

[BibT_eX]

[DOI]

Demid Borodin

Ben H. H. Juurlink

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Computer Architecture Techniques for Power-Efficiency

[BibT_eX]

[DOI]

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01721-6, 2008

Non deterministic caches: a simple and effective defense against side channel attacks.

[BibT_eX]

[DOI]

Alexandros Antonopoulos

Dimitrios N. Serpanos

Des. Autom. Embed. Syst., 2008

Low power microarchitecture with instruction reuse.

[BibT_eX]

[DOI]

Proceedings of the 5th Conference on Computing Frontiers, 2008

2007

Cache replacement based on reuse-distance prediction.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

Applying Decay to Reduce Dynamic Power in Set-Associative Caches.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Using value locality to reduce memory encryption overhead in embedded processors.

[BibT_eX]

[DOI]

Alexandros Antonopoulos

Dimitrios N. Serpanos

Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007

Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors.

[BibT_eX]

[DOI]

Proceedings of the 4th Conference on Computing Frontiers, 2007

2006

Preventing Denial-of-Service Attacks in Shared CMP Caches.

[BibT_eX]

[DOI]

Alexandros Antonopoulos

Dimitrios N. Serpanos

Proceedings of the Embedded Computer Systems: Architectures, 2006

Modeling Cache Sharing on Chip Multiprocessor Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

Topic 18: Embedded Parallel Systems.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

Dynamic Dictionary-Based Data Compression for Level-1 Caches.

[BibT_eX]

[DOI]

Konstantinos Aisopos

Proceedings of the Architecture of Computing Systems, 2006

2005

A simple mechanism to adapt leakage-control policies to temperature.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

IPStash: a set-associative memory approach for efficient IP-lookup.

[BibT_eX]

[DOI]

Proceedings of the INFOCOM 2005. 24th Annual Joint Conference of the IEEE Computer and Communications Societies, 2005

2004

Implementing branch-predictor decay using quasi-static memory cells.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2004

4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003

IPStash: a Power-Efficient Memory Architecture for IP-lookup.

[BibT_eX]

[DOI]

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

TCP: Tag Correlating Prefetchers.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002

Let caches decay: reducing leakage energy via exploitation of cache generational behavior.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2002

Implementing Decay Techniques using 4T Quasi-Static Memory Cells.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2002

Managing leakage for transient data: decay and quasi-static 4T memory cells.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

2001

Cache decay: exploiting generational behavior to reduce cache leakage power.

[BibT_eX]

[DOI]

Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Conference on Compilers, 2001

2000

Distributed vector architectures.

[BibT_eX]

[DOI]

J. Syst. Archit., 2000

Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power.

[BibT_eX]

[DOI]

Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Coherence Communication Prediction in Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

Cliff Young

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1999

DataScalar: A memory-centric approach to computing.

[BibT_eX]

[DOI]

Doug Burger

J. Syst. Archit., 1999

Improving CC-NUMA Performance Using Instruction-Based Prediction.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998

A Study of Three Dynamic Approaches to Handle Widely Shared Data in Shared-memory Multiprocessors.

[BibT_eX]

[DOI]

Stein Gjessing

Proceedings of the 12th international conference on Supercomputing, 1998

1997

DataScalar Architectures.

[BibT_eX]

[DOI]

Doug Burger

Proceedings of the 24th International Symposium on Computer Architecture, 1997

1996

Kiloprocessor Extensions to SCI.

[BibT_eX]

[DOI]

Proceedings of IPPS '96, 1996

The GLOW Cache Coherence Protocol Extensions for Widely Shared Data.

[BibT_eX]

[DOI]

Proceedings of the 10th international conference on Supercomputing, 1996

1992

PSM: software tool for simulating, prototyping, and monitoring of multiprocessor systems.

[BibT_eX]

[DOI]

Andreas Stafylopatis

I. Papakonstantinou

George K. Papakonstantinou

Inf. Softw. Technol., 1992

1991

A Prolog-based design environment for the high-level synthesis of application-specific architectures.

[BibT_eX]

[DOI]

Panagiotis Tsanakas