Stefano Di Matteo

Orcid: 0000-0002-5711-432X

According to our database1, Stefano Di Matteo authored at least 16 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
On hardware acceleration of quantum-resistant FOTA systems in automotive.
Comput. Electr. Eng., 2024

CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms.
IEEE Access, 2024

HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement.
IEEE Access, 2024

RTL Flow for the Power Side-Channel Resilience Assessment of a Post-Quantum SHA-3 Accelerator.
Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024

2023
Innovative Plug-and-Play System for Electrification of Wheel-Chairs.
IEEE Access, 2023

VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library.
IEEE Access, 2023

Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures.
Proceedings of the 8th South-East Europe Design Automation, 2023

Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

A PUF-Based Secure Boot for RISC-V Architectures.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

2022
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source.
Entropy, 2022

Design and Implementation on FPGA of a HW Accelerator for Post-Quantum RLWE Polynomial Operations.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

2021
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative.
Microprocess. Microsystems, November, 2021

A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms.
IEEE Access, 2021

CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2021

2019
Crypto Accelerators for Power-Efficient and Real-Time on-Chip Implementation of Secure Algorithms.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019


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