Stefano Di Carlo

Orcid: 0000-0002-7512-5356

Affiliations:
  • Politecnico di Torino, Italy


According to our database1, Stefano Di Carlo authored at least 212 papers between 2000 and 2024.

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Bibliography

2024
Biology System Description Language (BiSDL): a modeling language for the design of multicellular synthetic biological systems.
BMC Bioinform., December, 2024

CAN-MM: Multiplexed Message Authentication Code for Controller Area Network Message Authentication in Road Vehicles.
IEEE Trans. Veh. Technol., October, 2024

Neuronal Spike Shapes (NSS): A straightforward approach to investigate heterogeneity in neuronal excitability states.
Comput. Biol. Medicine, January, 2024

A methodology combining reinforcement learning and simulation to optimize the in silico culture of epithelial sheets.
J. Comput. Sci., 2024

Security and RAS in the Computing Continuum.
CoRR, 2024

Neuromorphic Heart Rate Monitors: Neural State Machines for Monotonic Change Detection.
CoRR, 2024

Can social media shape the security of next-generation connected vehicles?
CoRR, 2024

Vitamin-V: Expanding Open-Source RISC-V Cloud Environments.
CoRR, 2024

Hardware-based stack buffer overflow attack detection on RISC-V architectures.
CoRR, 2024

R-CONV: An Analytical Approach for Efficient Data Reconstruction via Convolutional Gradients.
CoRR, 2024

SpikeExplorer: hardware-oriented Design Space Exploration for Spiking Neural Networks on FPGA.
CoRR, 2024

Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge.
CoRR, 2024

A Survey on Hardware-Based Malware Detection Approaches.
IEEE Access, 2024

R-CONV: An Analytical Approach for Efficient Data Reconstruction via Convolutional Gradients.
Proceedings of the Web Information Systems Engineering - WISE 2024, 2024

Innovative Practices Track: Session 4 AI Applications in Test.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

A Micro Architectural Events Aware Real-Time Embedded System Fault Injector.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

CARACAS: vehiCular ArchitectuRe for detAiled Can Attacks Simulation.
Proceedings of the IEEE Symposium on Computers and Communications, 2024

Can social media shape the security of next-generation connected vehicles?
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

Navigating the road to automotive cybersecurity compliance.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

SpikingJET: Enhancing Fault Injection for Fully and Convolutional Spiking Neural Networks.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

Special Session: Security and RAS in the Computing Continuum.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024


2023
Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services.
CoRR, 2023

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
CoRR, 2023

A survey of hardware-based malware detection approach.
CoRR, 2023

Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Meta-analysis of Gene Activity (MAGA) Contributions and Correlation with Gene Expression, Through GAGAM.
Proceedings of the Bioinformatics and Biomedical Engineering, 2023


Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary study.
Proceedings of the IEEE European Test Symposium, 2023

Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective.
Proceedings of the IEEE European Test Symposium, 2023

Design Space Exploration of Approximate Computing Techniques with a Reinforcement Learning Approach.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

PSP Framework: A novel risk assessment method in compliance with ISO/SAE-21434.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023


GRAIGH: Gene Regulation accessibility integrating GeneHancer database.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2023

Optimization of synthetic oscillatory biological networks through Reinforcement Learning.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2023

2022
Test Technology Newsletter.
J. Electron. Test., 2022

TTTC News.
IEEE Des. Test, 2022

Fast Exploration of the Impact of Precision Reduction on Spiking Neural Networks.
CoRR, 2022

Are micro-architectural features able to explain faulty executions in the presence of soft errors? A preliminary study.
CoRR, 2022

CAN-MM: Multiplexed Message Authentication Code for Controller Area Network message authentication in road vehicles.
CoRR, 2022

FPGA-optimized Hardware acceleration for Spiking Neural Networks.
CoRR, 2022

Prediction of the Impact of Approximate Computing on Spiking Neural Networks via Interval Arithmetic.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

GAGAM: A Genomic Annotation-Based Enrichment of scATAC-seq Data for Gene Activity Matrix.
Proceedings of the Bioinformatics and Biomedical Engineering, 2022

A Methodology for Co-simulation-Based Optimization of Biofabrication Protocols.
Proceedings of the Bioinformatics and Biomedical Engineering, 2022

Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

LIN-MM: Multiplexed Message Authentication Code for Local Interconnect Network message authentication in road vehicles.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Artificial Resilience in neuromorphic systems.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

Toward the hardening of real-time operating systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

High-resolution sample size enrichment of single-cell multi-modal low-throughput Patch-seq datasets.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2022

Input-Aware Approximate Computing.
Proceedings of the IEEE International Conference on Automation, 2022

Using Analog Scrambling Circuits for Automotive Sensor Integrity and Authenticity.
Proceedings of the IEEE International Conference on Automation, 2022

2021
Guest Editorial: Special Section on Emerging Trends and Computing Paradigms for Testing, Reliability and Security in Future VLSI Systems.
IEEE Trans. Emerg. Top. Comput., 2021

EXT-TAURUM P2T: an Extended Secure CAN-FD Architecture for Road Vehicles.
CoRR, 2021

Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

TAURUM P2T: Advanced Secure CAN-FD Architecture for Road Vehicle.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Mitigation of Automotive Control Modules Hardware Replacement-based Attacks Through Hardware Signature.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021

Efficient Neural Network Approximation via Bayesian Reasoning.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Exploring Deep Learning for In-Field Fault Detection in Microprocessors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Meta-Analysis of cortical inhibitory interneurons markers landscape and their performances in scRNA-seq studies.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2021

2020
Guest Editors' Introduction: Selected Papers from IEEE VLSI Test Symposium.
IEEE Des. Test, 2020

An On-Line Testing Technique for the Scheduler Memory of a GPGPU.
IEEE Access, 2020

Integrating Online Safety-related Memory Tests in Multicore Real-Time Systems.
Proceedings of the 41st IEEE Real-Time Systems Symposium, 2020

Technology-Enhanced Learning (TEL) in Anaesthesia: Ultrasound Simulation Training for Innovative Locoregional Anaesthesia.
Proceedings of the Methodologies and Intelligent Systems for Technology Enhanced Learning, 2020

Design, Verification, Test and In-Field Implications of Approximate Computing Systems.
Proceedings of the IEEE European Test Symposium, 2020

Cross-Layer Soft-Error Resilience Analysis of Computing Systems.
Proceedings of the 50th Annual IEEE-IFIP International Conference on Dependable Systems and Networks, 2020

2019
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
IEEE Trans. Computers, 2019

Securing Soft IP Cores in FPGA based Reconfigurable Mobile Heterogeneous Systems.
CoRR, 2019

'One DB to rule them all' - the RING: a Regulatory INteraction Graph combining TFs, genes/proteins, SNPs, diseases and drugs.
Database J. Biol. Databases Curation, 2019

Bayesian models for early cross-layer reliability analysis and design space exploration.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Approximate computing design exploration through data lifetime metrics.
Proceedings of the 24th IEEE European Test Symposium, 2019

Alternatives to Fault Injections for Early Safety/Security Evaluations.
Proceedings of the 24th IEEE European Test Symposium, 2019

Combining Cluster Sampling and ACE analysis to improve fault-injection based reliability evaluation of GPU-based systems.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

On the in-field test of the GPGPU scheduler memory.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018
ReDO: Cross-Layer Multi-Objective Design-Exploration Framework for Efficient Soft Error Resilient Systems.
IEEE Trans. Computers, 2018

Multi-faceted microarchitecture level reliability characterization for NVIDIA and AMD GPUs.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Special session: How approximate computing impacts verification, test and reliability.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Predicting the Impact of Functional Approximation: from Component- to Application-Level.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Shielding Performance Monitor Counters: a double edged weapon for safety and security.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Trading-off reliability and performance in FPGA-based reconfigurable heterogeneous systems.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Modeling biological complexity using Biology System Description Language (BiSDL).
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2018

Securing bitstream integrity, confidentiality and authenticity in reconfigurable mobile heterogeneous systems.
Proceedings of the IEEE International Conference on Automation, 2018

2017
Innovative practices session 5C automotive test solutions.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Innovative practices session 9C DFT and data for diagnostics.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Microarchitecture level reliability comparison of modern GPU designs: First findings.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

SIFI: AMD southern islands GPU microarchitectural level fault injector.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Side-channel analysis of SEcube™ platform.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2017

Using multi-level Petri nets models to simulate microbiota resistance to antibiotics.
Proceedings of the 2017 IEEE International Conference on Bioinformatics and Biomedicine, 2017

2016
SIERRA - Simulation environment for memory redundancy algorithms.
Simul. Model. Pract. Theory, 2016

CyTRANSFINDER: a Cytoscape 3.3 plugin for three-component (TF, gene, miRNA) signal transduction pathway construction.
BMC Bioinform., 2016

Using Nets-Within-Nets for Modeling Differentiating Cells in the Epigenetic Landscape.
Proceedings of the Bioinformatics and Biomedical Engineering, 2016

Cross-layer system reliability assessment framework for hardware faults.
Proceedings of the 2016 IEEE International Test Conference, 2016

RIIF-2: Toward the next generation reliability information interchange format.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

A computationally inferred regulatory heart aging model including post-transcriptional regulations.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2016

FishAPP: A mobile App to detect fish falsification through image processing and machine learning techniques.
Proceedings of the IEEE International Conference on Automation, 2016

2015
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015

SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2015

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers.
ACM Trans. Embed. Comput. Syst., 2015

SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.
Microprocess. Microsystems, 2015

A cloud-based approach for Gene Regulatory Networks dynamics simulations.
Proceedings of the 4th Mediterranean Conference on Embedded Computing, 2015

A 3D Voxel Neighborhood Classification Approach within a Multiparametric MRI Classifier for Prostate Cancer Detection.
Proceedings of the Bioinformatics and Biomedical Engineering, 2015

Bayesian network early reliability evaluation analysis for both permanent and transient faults.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Power-aware voltage tuning for STT-MRAM reliability.
Proceedings of the 20th IEEE European Test Symposium, 2015

A Bayesian model for system level reliability estimation.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories.
ACM Trans. Archit. Code Optim., 2014

Using Boolean networks to model post-transcriptional regulation in gene regulatory networks.
J. Comput. Sci., 2014

Alice in "Bio-Land": Engineering Challenges in the World of Life Sciences.
IT Prof., 2014

FunMod: A Cytoscape Plugin for Identifying Functional Modules in Undirected Protein-Protein Networks.
Genom. Proteom. Bioinform., 2014

A Functional Approach for Testing the Reorder Buffer Memory.
J. Electron. Test., 2014

A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris.
EURASIP J. Adv. Signal Process., 2014

Cross-layer early reliability evaluation: Challenges and promises.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A novel methodology to increase fault tolerance in autonomous FPGA-based systems.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Integration of STT-MRAM model into CACTI simulator.
Proceedings of the 9th International Design and Test Symposium, 2014

Cross-Layer Early Reliability Evaluation for the Computing cOntinuum.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Reliability estimation at block-level granularity of spin-transfer-torque MRAMs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A Prostate Cancer Computer Aided Diagnosis Software including Malignancy Tumor Probabilistic Classification.
Proceedings of the BIOIMAGING 2014, 2014

A Computational Pipeline to Identify New Potential Regulatory Motifs in Melanoma Progression.
Proceedings of the Biomedical Engineering Systems and Technologies, 2014

A Computational Study to Identify TP53 and SREBF2 as Regulation Mediators of miR-214 in Melanoma Progression.
Proceedings of the BIOINFORMATICS 2014, 2014

Identifying Sub-Network Functional Modules in Protein Undirected Networks.
Proceedings of the BIOINFORMATICS 2014, 2014

2013
Design and optimization of adaptable BCH codecs for NAND flash memories.
Microprocess. Microsystems, 2013

A systematic analysis of a mi-RNA inter-pathway regulatory motif.
J. Clin. Bioinform., 2013

Accounting for Post-Transcriptional Regulation in Boolean Networks Based Regulatory Models.
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2013

A New miRNA Motif Protects Pathways Expression in Gene Regulatory Networks.
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2013

Fault mitigation strategies for CUDA GPUs.
Proceedings of the 2013 IEEE International Test Conference, 2013

Ef<sup>3</sup>S: An evaluation framework for flash-based systems.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Increasing the robustness of CUDA Fermi GPU-based systems.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

SAFE: A self adaptive frame enhancer FPGA-based IP-core for real-time space applications.
Proceedings of the 8th International Design and Test Symposium, 2013

ZipStream: Improving dependability in dynamic partial reconfiguration.
Proceedings of the 8th International Design and Test Symposium, 2013

FEMIP: A high performance FPGA-based features extractor & matcher for space applications.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A software-based self test of CUDA Fermi GPUs.
Proceedings of the 18th IEEE European Test Symposium, 2013

On the on-line functional test of the Reorder Buffer memory in superscalar processors.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

AIDI: An adaptive image denoising FPGA-based IP-core for real-time applications.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
FPGA-Based Remote-Code Integrity Verification of Programs in Distributed Embedded Systems.
IEEE Trans. Syst. Man Cybern. Part C, 2012

Statistical Reliability Estimation of Microprocessor-Based Systems.
IEEE Trans. Computers, 2012

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Combining homolog and motif similarity data with Gene Ontology relationships for protein function prediction.
Proceedings of the 2012 IEEE International Conference on Bioinformatics and Biomedicine, 2012

2011
A cDNA Microarray Gene Expression Data Classifier for Clinical Diagnostics Based on Graph Theory.
IEEE ACM Trans. Comput. Biol. Bioinform., 2011

Software-Based Self-Test of Set-Associative Cache Memories.
IEEE Trans. Computers, 2011

Increasing pattern recognition accuracy for chemical sensing by evolutionary based drift compensation.
Pattern Recognit. Lett., 2011

Efficient multi-level fault simulation of HW/SW systems for structural faults.
Sci. China Inf. Sci., 2011

Building gene expression profile classifiers with a simple and efficient rejection option in R.
BMC Bioinform., 2011

Exploiting code mobility for dynamic binary obfuscation.
Proceedings of the 2011 World Congress on Internet Security, 2011

An area-efficient 2-D convolution implementation on FPGA for space applications.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Validation & Verification of an EDA automated synthesis tool.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

A unifying formalism to support automated synthesis of SBSTs for embedded caches.
Proceedings of the 9th East-West Design & Test Symposium, 2011

Genetic Defect Based March Test Generation for SRAM.
Proceedings of the Applications of Evolutionary Computation, 2011

MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
System reliability evaluation using concurrent multi-level simulation of structural faults.
Proceedings of the 2011 IEEE International Test Conference, 2010

Towards drift correction in chemical sensors using an evolutionary strategy.
Proceedings of the Genetic and Evolutionary Computation Conference, 2010

EDACs and test integration strategies for NAND flash memories.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Exploring modeling and testing of NAND flash memories.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Exploiting Evolution for an Adaptive Drift-Robust Classifier in Chemical Sensing.
Proceedings of the Applications of Evolutionary Computation, 2010

Microprocessor fault-tolerance via on-the-fly partial reconfiguration.
Proceedings of the 15th European Test Symposium, 2010

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Are IEEE-1500-Compliant Cores Really Compliant to the Standard?.
IEEE Des. Test Comput., 2009

Test infrastructures evaluation at transaction level.
Proceedings of the 2009 IEEE International Test Conference, 2009

FLARE: A design environment for FLASH-based space applications.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

System Level Testing via TLM 2.0 Debug Transport Interface.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Test exploration and validation using transaction level models.
Proceedings of the Design, Automation and Test in Europe, 2009

A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
IEEE Standard 1500 Compliance Verification for Embedded Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2008

March Test Generation Revealed.
IEEE Trans. Computers, 2008

"Plug & Test" at System Level via Testable TLM Primitives.
Proceedings of the 2008 IEEE International Test Conference, 2008

Automating defects simulation and fault modeling for SRAMs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Functional testing approaches for "BIFST-able" tlm_fifo.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Applying March Tests to K-Way Set-Associative Cache Memories.
Proceedings of the 13th European Test Symposium, 2008

A graph-based representation of Gene Expression profiles in DNA microarrays.
Proceedings of the 2008 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2008

Differential gene expression graphs: A data structure for classification in DNA microarrays.
Proceedings of the 8th IEEE International Conference on Bioinformatics and Bioengineering, 2008

Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-Cells.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

On-Line Instruction-Checking in Pipelined Microprocessors.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs.
IET Comput. Digit. Tech., 2007

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Automating the IEEE std.1500 compliance verification for embedded cores.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

A Functional Verification Based Fault Injection Environment.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Single-Event Upset Analysis and Protection in High Speed Circuits.
Proceedings of the 11th European Test Symposium, 2006

A 22n March Test for Realistic Static Linked Faults in SRAMs.
Proceedings of the 11th European Test Symposium, 2006

Automatic March Tests Generation for Multi-Port SRAMs.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Automatic march tests generations for static linked faults in SRAMs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

ATPG for Dynamic Burn-In Test in Full-Scan Circuits.
Proceedings of the 15th Asian Test Symposium, 2006

Memory Fault Simulator for Static-Linked Faults.
Proceedings of the 15th Asian Test Symposium, 2006

2005
March AB, March AB1: new March tests for unlinked dynamic memory faults.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Automatic March tests generation for static and dynamic faults in SRAMs.
Proceedings of the 10th European Test Symposium, 2005

2004
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003
Infrastructures and algorithms for testable and dependable systems-on-a-chip.
PhD thesis, 2003

A Hierarchical Infrastructure for SoC Test Management.
IEEE Des. Test Comput., 2003

Online Self-Repair of FIR Filters.
IEEE Des. Test Comput., 2003

Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures.
IEEE Commun. Mag., 2003

Test Engineering Education in Europe: the EuNICE-Test Project.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Data Critically Estimation In Software Applications.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FAUST: FAUlt-injection Script-based Tool.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

A Watchdog Processor to Detect Data and Control Flow Errors.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

2002
Static Analysis of SEU Effects on Software Applications.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Automated Synthesis of SEU Tolerant Architectures from OO Descriptions.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

An Optimal Algorithm for the Automatic Generation of March Tests.
Proceedings of the 2002 Design, 2002

Specification and Design of a New Memory Fault Simulator.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Validation of a Software Dependability Tool via Fault Injection Experiments.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

On applying the set covering model to reseeding.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

SEU effect analysis in an open-source router via a distributed fault injection environment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Control-Flow Checking via Regular Expressions.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Memory Read Faults: Taxonomy and Automatic Test Generation.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
A programmable BIST architecture for clusters of multiple-port SRAMs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

HD<sup>2</sup>BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

An effective distributed BIST architecture for RAMs.
Proceedings of the 5th European Test Workshop, 2000


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