Stefania Perri

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

2023

FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis.

[BibT_eX]

[DOI]

Robert J. Stewart

J. Signal Process. Syst., October, 2023

Design of Leading Zero Counters on FPGAs.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., September, 2023

A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.

[BibT_eX]

[DOI]

CoRR, 2023

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms.

[BibT_eX]

[DOI]

CoRR, 2023

Design of Approximate Bilateral Filters for Image Denoising on FPGAs.

[BibT_eX]

[DOI]

IEEE Access, 2023

2022

Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Multibit Full Comparator Logic in Quantum-Dot Cellular Automata.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes.

[BibT_eX]

[DOI]

Sensors, 2022

Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems.

[BibT_eX]

[DOI]

IEEE Access, 2022

Runtime Reconfigurable Hardware Accelerator for Energy-Efficient Transposed Convolutions.

[BibT_eX]

[DOI]

Emanuel Marrazzo

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Accuracy Evaluation of Transposed Convolution-Based Quantized Neural Networks.

[BibT_eX]

[DOI]

Robert J. Stewart

Proceedings of the International Joint Conference on Neural Networks, 2022

Design-Space Exploration of Quantized Transposed Convolutional Neural Networks for FPGA-based Systems-on-Chip.

[BibT_eX]

[DOI]

Robert J. Stewart

Proceedings of the IEEE Intl. Conf. on Dependable, 2022

2021

Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions.

[BibT_eX]

[DOI]

J. Imaging, 2021

2020

Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Stereo vision architecture for heterogeneous systems-on-chip.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2020

Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip.

[BibT_eX]

[DOI]

J. Imaging, 2020

Design of a real-time face detection architecture for heterogeneous systems-on-chips.

[BibT_eX]

[DOI]

Integr., 2020

Parallel architecture of power-of-two multipliers for FPGAs.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2020

Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis.

[BibT_eX]

[DOI]

Sensors, 2019

Multimodal background subtraction for high-performance embedded systems.

[BibT_eX]

[DOI]

Lorena-de-los-Angeles Guachi-Guachi

J. Real Time Image Process., 2019

Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

2018

Design of Real-Time FPGA-based Embedded System for Stereo Vision.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Designing Fast Convolutional Engines for Deep Learning Applications.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Design of Efficient BCD Adders in Quantum-Dot Cellular Automata.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016

An efficient hardware-oriented stereo matching algorithm.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Design of efficient QCA multiplexers.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2016

2015

Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Power supply noise in accurate delay model for the sub-threshold domain.

[BibT_eX]

[DOI]

Integr., 2015

Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014

Area-Delay Efficient Binary Adders in QCA.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2014

Analyzing noise robustness of wide fan-in dynamic logic gates under process variations.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2014

Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2014

A novel background subtraction method based on color invariants and grayscale levels.

[BibT_eX]

[DOI]

Proceedings of the International Carnahan Conference on Security Technology, 2014

2013

Adaptive Census Transform: A novel hardware-oriented stereovision algorithm.

[BibT_eX]

[DOI]

Comput. Vis. Image Underst., 2013

2012

Low-Power Level Shifter for Multi-Supply Voltage Designs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Analytical Delay Model Considering Variability Effects in Subthreshold Domain.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Comparative analysis of yield optimized pulsed flip-flops.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

Low-cost FPGA stereo vision system for real time disparity maps calculation.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2012

Energy-efficient single-clock-cycle binary comparator.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2012

2011

Fast-squarer circuits using 3-bit-scan without overlapping bits.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2011

Efficient memory architecture for image processing.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2011

2010

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2010

Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Impact of Process Variations on Flip-Flops Energy and Timing Characteristics.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A new low-power high-speed single-clock-cycle binary comparator.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Designing High-Speed Adders in Power-Constrained Environments.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems.

[BibT_eX]

[DOI]

J. Low Power Electron., 2009

Low-power split-path data-driven dynamic logic.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2009

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2009

2008

Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2008

A matrix product accelerator for field programmable systems on chip.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2008

High-performance noise-tolerant circuit techniques for CMOS dynamic logic.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2008

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

VLSI implementations of efficient isotropic flexible 2D convolvers.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2007

MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2007

An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Design and Implementation of a 90nm Low bit-rate Image Compression Core.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications.

[BibT_eX]

[DOI]

Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006

Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Low bit rate image compression core for onboard space applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2006

Simd Multipliers for Accelerating Embedded Processors in FPGAS.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2006

Leakage energy reduction techniques in deep submicron cache memories: a comparative study.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An integrated countermeasure against differential power analysis for secure smart-cards.

[BibT_eX]

[DOI]

Martin Margala

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs.

[BibT_eX]

[DOI]

Paolo Zicari

Proceedings of the 13th IEEE International Conference on Electronics, 2006

SAD-Based Stereo Matching Circuit for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

Efficient Addition Circuits for Modular Design of Processors-in-Memory.

[BibT_eX]

[DOI]

Martin Margala

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A high-performance fully reconfigurable FPGA-based 2D convolution processor.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2005

Microprocessor-based FPGA implementation of SPIHT image compression subsystems.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2005

Efficient Reconfigurable Manchester Adders for Low-power Media Processing.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2005

Fast Low-Power 64-Bit Modular Hybrid Adder.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

Variable precision arithmetic circuits for FPGA-based multimedia processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Area- and Power-Reduced Standard-Cell Spanning Tree Adders.

[BibT_eX]

Vitit Kantabutra

Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003

A high-speed energy-efficient 64-bit reconfigurable binary adder.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

A low-power sub-nanosecond standard-cells based adder.

[BibT_eX]

[DOI]

Giovanni Staino

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002

VLSI circuits for low-power high-speed asynchronous addition.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Speed-efficient wide adders for VIRTEX FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Dynamic power of CMOS gates driving lossy transmission lines.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Area-time-power tradeoff in cellular arrays VLSI implementations.

[BibT_eX]

[DOI]

G. Cororullo

IEEE Trans. Very Large Scale Integr. Syst., 2000

VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

Designing High-Speed Asynchronous Pipelines.

[BibT_eX]

[DOI]

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999

A 56-bit self-timed adder for high speed asynchronous datapath.

[BibT_eX]

[DOI]