Stefan Rusu
Orcid: 0000-0002-3322-9173
According to our database1,
Stefan Rusu
authored at least 35 papers
between 1993 and 2020.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2007, "For contributions to high performance microprocessor circuit technologies".
Timeline
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Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
IEEE J. Solid State Circuits, 2020
2019
Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2019
A 7nm 4GHz Arm<sup>®</sup>-core-based CoWoS<sup>®</sup> Chiplet Design for High Performance Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2016
Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
2015
IEEE J. Solid State Circuits, 2015
Introduction to the Special Section on the 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2015
2014
Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2010
2009
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007).
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series.
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
IEEE J. Solid State Circuits, 2005
A 130-nm triple-V<sub>t</sub> 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor.
IEEE J. Solid State Circuits, 2005
2004
Proceedings of the 2004 International Symposium on System-on-Chip, 2004
2003
IEEE J. Solid State Circuits, 2003
Proceedings of the 40th Design Automation Conference, 2003
2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
2000
IEEE J. Solid State Circuits, 2000
Proceedings of the 2000 International Symposium on Physical Design, 2000
1993
Proceedings of the European Design Automation Conference 1993, 1993