Stefan Metzlaff

According to our database, Stefan Metzlaff authored at least 13 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Accelerating Automated Driving and ADAS Using HW/SW Codesign.

Shubham Rai, Cecilia De la Parra, Martin Rapp, Jan Micha Borrmann, Nina Bretz, Stefan Metzlaff, Taha Soliman, Christoph Schorn

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

2014

A comparison of instruction memories from the WCET perspective.

Stefan Metzlaff, Theo Ungerer

J. Syst. Archit., 2014

Exploiting Intel TSX for fault-tolerant execution in safety-critical systems.

Florian Haas, Sebastian Weis, Stefan Metzlaff, Theo Ungerer

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

A hard real-time capable multi-core SMT processor.

Marco Paolieri, Jörg Mische, Stefan Metzlaff, Mike Gerdes, Eduardo Quiñones, Sascha Uhrig, Theo Ungerer, Francisco J. Cazorla

ACM Trans. Embed. Comput. Syst., 2013

Leveraging transactional memory for a predictable execution of applications composed of hard real-time and best-effort tasks.

Stefan Metzlaff, Sebastian Weis, Theo Ungerer

Proceedings of the 21st International Conference on Real-Time Networks and Systems, 2013

2012

Analysable instruction memories for hard real-time systems.

Stefan Metzlaff

PhD thesis, 2012

Impact of Instruction Cache and Different Instruction Scratchpads on the WCET Estimate.

Stefan Metzlaff, Theo Ungerer

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Replacement Policies for a Function-Based Instruction Memory: A Quantification of the Impact on Hardware Complexity and WCET Estimates.

Stefan Metzlaff, Theo Ungerer

Proceedings of the 24th Euromicro Conference on Real-Time Systems, 2012

2011

RTOS support for execution of parallelized hard real-time tasks on the MERASA multi-core processor.

Julian Wolf, Mike Gerdes, Florian Kluge, Sascha Uhrig, Jörg Mische, Stefan Metzlaff, Christine Rochange, Hugues Cassé, Pascal Sainrat, Theo Ungerer

Comput. Syst. Sci. Eng., 2011

A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware.

Stefan Metzlaff, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer

Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

2010

Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability.

Theo Ungerer, Francisco J. Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quiñones, Mike Gerdes, Marco Paolieri, Julian Wolf, Hugues Cassé, Sascha Uhrig, Irakli Guliashvili, Michael Houston, Florian Kluge, Stefan Metzlaff, Jörg Mische

IEEE Micro, 2010

RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor.

Julian Wolf, Mike Gerdes, Florian Kluge, Sascha Uhrig, Jörg Mische, Stefan Metzlaff, Christine Rochange, Hugues Cassé, Pascal Sainrat, Theo Ungerer

Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2010

2008

Predictable dynamic instruction scratchpad for simultaneous multithreaded processors.

Stefan Metzlaff, Sascha Uhrig, Jörg Mische, Theo Ungerer

Proceedings of the 9th workshop on MEmory performance, 2008