Stefan Mangard

Orcid: 0000-0001-9650-8041

Affiliations:
  • Graz University of Technology, Austria


According to our database1, Stefan Mangard authored at least 149 papers between 2001 and 2024.

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Bibliography

2024
Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Quantile: Quantifying Information Leakage.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low Latency.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Compress: Generate Small and Fast Masked Pipelined Circuits.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

TME-Box: Scalable In-Process Isolation through Intel TME-MK Memory Encryption.
CoRR, 2024

SLUBStick: Arbitrary Memory Writes through Practical Software Cross-Cache Attacks within the Linux Kernel.
Proceedings of the 33rd USENIX Security Symposium, 2024

Defects-in-Depth: Analyzing the Integration of Effective Defenses against One-Day Exploits in Android Kernels.
Proceedings of the 33rd USENIX Security Symposium, 2024

Voodoo: Memory Tagging, Authenticated Encryption, and Error Correction through MAGIC.
Proceedings of the 33rd USENIX Security Symposium, 2024

Exact Soft Analytical Side-Channel Attacks using Tractable Circuits.
Proceedings of the Forty-first International Conference on Machine Learning, 2024

Security Aspects of Masking on FPGAs.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

Memory Tagging using Cryptographic Integrity on Commodity x86 CPUs.
Proceedings of the 9th IEEE European Symposium on Security and Privacy, 2024

Beyond the Edges of Kernel Control-Flow Hijacking Protection with HEK-CFI.
Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024

2023
Secure Context Switching of Masked Software Implementations.
IACR Cryptol. ePrint Arch., 2023

Compress: Reducing Area and Latency of Masked Pipelined Circuits.
IACR Cryptol. ePrint Arch., 2023

HashTag: Hash-based Integrity Protection for Tagged Architectures.
Proceedings of the 32nd USENIX Security Symposium, 2023

Collide+Power: Leaking Inaccessible Data with Software-based Power Side Channels.
Proceedings of the 32nd USENIX Security Symposium, 2023

Scatter and Split Securely: Defeating Cache Contention and Occupancy Attacks.
Proceedings of the 44th IEEE Symposium on Security and Privacy, 2023

MEMES: Memory Encryption-Based Memory Safety on Commodity Hardware.
Proceedings of the 20th International Conference on Security and Cryptography, 2023

EC-CFI: Control-Flow Integrity via Code Encryption Counteracting Fault Attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

SCRAMBLE-CFI: Mitigating Fault-Induced Control-Flow Attacks on OpenTitan.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

SCFI: State Machine Control-Flow Hardening Against Fault Attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Cryptographically Enforced Memory Safety.
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023

Multi-Tag: A Hardware-Software Co-Design for Memory Safety based on Multi-Granular Memory Tagging.
Proceedings of the 2023 ACM Asia Conference on Computer and Communications Security, 2023

SPEAR-V: Secure and Practical Enclave Architecture for RISC-V.
Proceedings of the 2023 ACM Asia Conference on Computer and Communications Security, 2023

DOPE: DOmain Protection Enforcement with PKS.
Proceedings of the Annual Computer Security Applications Conference, 2023

2022
SYNFI: Pre-Silicon Fault Analysis of an Open-Source Secure Element.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Riding the Waves Towards Generic Single-Cycle Masking in Hardware.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Formal Verification of Arithmetic Masking in Hardware and Software.
IACR Cryptol. ePrint Arch., 2022

Power Contracts: Provably Complete Power Leakage Models for Processors.
IACR Cryptol. ePrint Arch., 2022

Jenny: Securing Syscalls for PKU-based Memory Isolation Systems.
Proceedings of the 31st USENIX Security Symposium, 2022

SFP: Providing System Call Flow Protection against Software and Fault Attacks.
Proceedings of the 11th International Workshop on Hardware and Architectural Support for Security and Privacy, 2022

FIPAC: Thwarting Fault- and Software-Induced Control-Flow Attacks with ARM Pointer Authentication.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2022

2021
Secure and Efficient Software Masking on Superscalar Pipelined Processors.
IACR Cryptol. ePrint Arch., 2021

SecWalk: Protecting Page Table Walks Against Fault Attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

Protecting Indirect Branches Against Fault Attacks Using ARM Pointer Authentication.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

SERVAS! Secure Enclaves via RISC-V Authenticryption Shield.
Proceedings of the Computer Security - ESORICS 2021, 2021

HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment.
Proceedings of the ASIA CCS '21: ACM Asia Conference on Computer and Communications Security, 2021

CrypTag: Thwarting Physical and Logical Memory Vulnerabilities using Cryptographically Colored Memory.
Proceedings of the ASIA CCS '21: ACM Asia Conference on Computer and Communications Security, 2021

2020
Isap v2.0.
IACR Trans. Symmetric Cryptol., 2020

Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs.
IACR Cryptol. ePrint Arch., 2020

Malware Guard Extension: abusing Intel SGX to conceal cache attacks.
Cybersecur., 2020

Meltdown: reading kernel memory from user space.
Commun. ACM, 2020

Spectre attacks: exploiting speculative execution.
Commun. ACM, 2020

Donky: Domain Keys - Efficient In-Process Isolation for RISC-V and x86.
Proceedings of the 29th USENIX Security Symposium, 2020

2019
MEAS: memory encryption and authentication secure against side-channel attacks.
J. Cryptogr. Eng., 2019

Small Faults Grow Up - Verification of Error Masking Robustness in Arithmetically Encoded Programs.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2019

ScatterCache: Thwarting Cache Attacks via Cache Set Randomization.
Proceedings of the 28th USENIX Security Symposium, 2019

TIMBER-V: Tag-Isolated Memory Bringing Fine-grained Enclaves to RISC-V.
Proceedings of the 26th Annual Network and Distributed System Security Symposium, 2019

Protecting RISC-V Processors against Physical Attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

First-Order Masking with Only Two Random Bits.
Proceedings of ACM Workshop on Theory of Implementation Security, 2019

2018
Spectre Attacks: Exploiting Speculative Execution.
meltdownattack.com, 2018

Meltdown
meltdownattack.com, 2018

SIFA: Exploiting Ineffective Fault Inductions on Symmetric Cryptography.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

A unified masking approach.
J. Cryptogr. Eng., 2018

Masking the AES with Only Two Random Bits.
IACR Cryptol. ePrint Arch., 2018

Fault Attacks on Nonce-based Authenticated Encryption: Application to Keyak and Ketje.
IACR Cryptol. ePrint Arch., 2018

Exploiting Ineffective Fault Inductions on Symmetric Cryptography.
IACR Cryptol. ePrint Arch., 2018

Statistical Ineffective Fault Attacks on Masked AES with Fault Countermeasures.
IACR Cryptol. ePrint Arch., 2018

Sharing Independence & Relabeling: Efficient Formal Verification of Higher-Order Masking.
IACR Cryptol. ePrint Arch., 2018

Systematic Classification of Side-Channel Attacks: A Case Study for Mobile Devices.
IEEE Commun. Surv. Tutorials, 2018

SCAnDroid: Automated Side-Channel Analysis of Android APIs.
Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks, 2018

DATA - Differential Address Trace Analysis: Finding Address-based Side-Channels in Binaries.
Proceedings of the 27th USENIX Security Symposium, 2018

Meltdown: Reading Kernel Memory from User Space.
Proceedings of the 27th USENIX Security Symposium, 2018

KeyDrown: Eliminating Software-Based Keystroke Timing Side-Channel Attacks.
Proceedings of the 25th Annual Network and Distributed System Security Symposium, 2018

DATA - Differential Address Trace Analysis.
Proceedings of the 28. Krypto-Tag, 2018

Sponge-Based Control-Flow Protection for IoT Devices.
Proceedings of the 2018 IEEE European Symposium on Security and Privacy, 2018

Securing conditional branches in the presence of fault attacks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

High speed ASIC implementations of leakage-resilient cryptography.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

ProcHarvester: Fully Automated Analysis of Procfs Side-Channel Leaks on Android.
Proceedings of the 2018 on Asia Conference on Computer and Communications Security, 2018

Automated Detection, Exploitation, and Elimination of Double-Fetch Bugs using Modern CPU Features.
Proceedings of the 2018 on Asia Conference on Computer and Communications Security, 2018

Pointing in the Right Direction - Securing Memory Accesses in a Faulty World.
Proceedings of the 34th Annual Computer Security Applications Conference, 2018

2017
ISAP - Towards Side-Channel Secure Authenticated Encryption.
IACR Trans. Symmetric Cryptol., 2017

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Dependable Internet of Things for Networked Cars.
Int. J. Comput., 2017

Transparent Memory Encryption and Authentication.
IACR Cryptol. ePrint Arch., 2017

Securing Memory Encryption and Authentication Against Side-Channel Attacks Using Unprotected Primitives.
IACR Cryptol. ePrint Arch., 2017

Leakage Bounds for Gaussian Side Channels.
IACR Cryptol. ePrint Arch., 2017

Single-Trace Side-Channel Attacks on Masked Lattice-Based Encryption.
IACR Cryptol. ePrint Arch., 2017

Higher-Order Side-Channel Protected Implementations of Keccak.
IACR Cryptol. ePrint Arch., 2017

Reconciling d+1Masking in Hardware and Software.
IACR Cryptol. ePrint Arch., 2017

Formal Verification of Masked Hardware Implementations in the Presence of Glitches.
IACR Cryptol. ePrint Arch., 2017

KeyDrown: Eliminating Keystroke Timing Side-Channel Attacks.
CoRR, 2017

Hello from the Other Side: SSH over Robust Cache Covert Channels in the Cloud.
Proceedings of the 24th Annual Network and Distributed System Security Symposium, 2017

Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.
Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, 2017

Fantastic Timers and Where to Find Them: High-Resolution Microarchitectural Attacks in JavaScript.
Proceedings of the Financial Cryptography and Data Security, 2017

KASLR is Dead: Long Live KASLR.
Proceedings of the Engineering Secure Software and Systems - 9th International Symposium, 2017

Practical Keystroke Timing Attacks in Sandboxed JavaScript.
Proceedings of the Computer Security - ESORICS 2017, 2017

Malware Guard Extension: Using SGX to Conceal Cache Attacks.
Proceedings of the Detection of Intrusions and Malware, and Vulnerability Assessment, 2017

An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order.
Proceedings of the Topics in Cryptology - CT-RSA 2017, 2017

Reconciling d+1 Masking in Hardware and Software.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2017, 2017

2016
Side-Channel Plaintext-Recovery Attacks on Leakage-Resilient Encryption.
IACR Cryptol. ePrint Arch., 2016

Exploiting the Physical Disparity: Side-Channel Attacks on Memory Encryption.
IACR Cryptol. ePrint Arch., 2016

Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order.
IACR Cryptol. ePrint Arch., 2016

Concealing Secrets in Embedded Processors Designs.
IACR Cryptol. ePrint Arch., 2016

ISAP - Authenticated Encryption Inherently Secure Against Passive Side-Channel Attacks.
IACR Cryptol. ePrint Arch., 2016

SoK: Systematic Classification of Side-Channel Attacks on Mobile Devices.
CoRR, 2016

Exploiting Data-Usage Statistics for Website Fingerprinting Attacks on Android.
Proceedings of the 9th ACM Conference on Security & Privacy in Wireless and Mobile Networks, 2016

DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks.
Proceedings of the 25th USENIX Security Symposium, 2016

ARMageddon: Cache Attacks on Mobile Devices.
Proceedings of the 25th USENIX Security Symposium, 2016

Flush+Flush: A Fast and Stealthy Cache Attack.
Proceedings of the Detection of Intrusions and Malware, and Vulnerability Assessment, 2016

Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript.
Proceedings of the Detection of Intrusions and Malware, and Vulnerability Assessment, 2016

Enhancing Side-Channel Analysis of Binary-Field Multiplication with Bit Reliability.
Proceedings of the Topics in Cryptology - CT-RSA 2016 - The Cryptographers' Track at the RSA Conference 2016, San Francisco, CA, USA, February 29, 2016

Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR.
Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016

2015
On the Security of Fresh Re-keying to Counteract Side-Channel and Fault Attacks.
IACR Cryptol. ePrint Arch., 2015

Reverse Engineering Intel DRAM Addressing and Exploitation.
CoRR, 2015

ARMageddon: Last-Level Cache Attacks on Mobile Devices.
CoRR, 2015

Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches.
Proceedings of the 24th USENIX Security Symposium, 2015

Fault Attacks at the System Level - The Challenge of Securing Application Software.
Proceedings of the 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2015

Practical Memory Deduplication Attacks in Sandboxed Javascript.
Proceedings of the Computer Security - ESORICS 2015, 2015

Protecting the Control Flow of Embedded Processors against Fault Attacks.
Proceedings of the Smart Card Research and Advanced Applications, 2015

Towards Fresh and Hybrid Re-Keying Schemes with Beyond Birthday Security.
Proceedings of the Smart Card Research and Advanced Applications, 2015

2014
Towards fresh re-keying with leakage-resilient PRFs: cipher design principles and analysis.
J. Cryptogr. Eng., 2014

2013
Keeping Secrets on Low-Cost Chips.
IEEE Secur. Priv., 2013

Clustering Algorithms for Non-Profiled Single-Execution Attacks on Exponentiations.
IACR Cryptol. ePrint Arch., 2013

On the Relationship between Correlation Power Analysis and the Stochastic Approach: An ASIC Designer Perspective.
Proceedings of the Progress in Cryptology - INDOCRYPT 2013, 2013

2012
Die physikalische Sicherheit eingebetteter Systeme.
Datenschutz und Datensicherheit, 2012

Localized Electromagnetic Analysis of Cryptographic Implementations.
Proceedings of the Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27, 2012

Exploiting the Difference of Side-Channel Leakages.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

2011
One for all - all for one: unifying standard differential power analysis attacks.
IET Inf. Secur., 2011

Arithmetic logic units with high error detection rates to counteract fault attacks.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
The World is Not Enough: Another Look on Second-Order DPA.
IACR Cryptol. ePrint Arch., 2010

On the Duality of Probing and Fault Attacks.
J. Electron. Test., 2010

Counteracting Power Analysis Attacks by Masking.
Proceedings of the Secure Integrated Circuits and Systems, 2010

2009
One for All - All for One: Unifying Standard DPA Attacks.
IACR Cryptol. ePrint Arch., 2009

Practical Attacks on Masked Hardware.
Proceedings of the Topics in Cryptology, 2009

2007
Power Analysis Attacks and Countermeasures.
IEEE Des. Test Comput., 2007

Tutorial T1: Designing Secure SoCs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Template Attacks on Masking - Resistance Is Futile.
Proceedings of the Topics in Cryptology, 2007

Evaluation of the Masked Logic Style MDPL on a Prototype Chip.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007

Power and EM Attacks on Passive 13.56 MHz RFID Devices.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007

Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis.
Proceedings of the Applied Cryptography and Network Security, 5th International Conference, 2007

Power analysis attacks - revealing the secrets of smart cards.
Springer, ISBN: 978-0-387-30857-9, 2007

2006
Investigations of Power Analysis Attacks and Countermeasures for ARIA.
Proceedings of the Information Security Applications, 7th International Workshop, 2006

Implementation aspects of the DPA-resistant logic style MDPL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Side channel analysis resistant design flow.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Practical Second-Order DPA Attacks for Masked Smart Card Implementations of Block Ciphers.
Proceedings of the Topics in Cryptology, 2006

Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

An AES Smart Card Implementation Resistant to Power Analysis Attacks.
Proceedings of the Applied Cryptography and Network Security, 4th International Conference, 2006

2005
A novel CMOS logic style with data independent power consumption.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Side-Channel Analysis Resistant Description of the AES S-Box.
Proceedings of the Fast Software Encryption: 12th International Workshop, 2005

Side-Channel Leakage of Masked CMOS Gates.
Proceedings of the Topics in Cryptology, 2005

Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

Successfully Attacking Masked AES Hardware Implementations.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004
Secure and Efficient Masking of AES - A Mission Impossible?
IACR Cryptol. ePrint Arch., 2004

Hardware Countermeasures against DPA ? A Statistical Analysis of Their Effectiveness.
Proceedings of the Topics in Cryptology, 2004

Efficient AES Implementations on ASICs and FPGAs.
Proceedings of the Advanced Encryption Standard - AES, 4th International Conference, 2004

2003
A Highly Regular and Scalable AES Hardware Architecture.
IEEE Trans. Computers, 2003

2002
A Simple Power-Analysis (SPA) Attack on Implementations of the AES Key Expansion.
Proceedings of the Information Security and Cryptology, 2002

2001
A new approach to DNS security (DNSSEC).
Proceedings of the CCS 2001, 2001


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