A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI.

[BibT_eX]

[DOI]

Seyed Mohammad Ali Zeinolabedin

Franz Marcus Schüffny

IEEE Trans. Biomed. Circuits Syst., 2022

A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm.

[BibT_eX]

[DOI]

Franz Marcus Schüffny

Stefan Hänzsche

Marc Berthel

Seyed Mohammad Ali Zeinolabedin

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

2021

Ultra-High Compression of Twiddle Factor ROMs in Multi-Core DSP for FMCW Radars.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System.

[BibT_eX]

[DOI]

Johannes Partzsch

Christian Mayr

Massimiliano Giulioni

J. Signal Process. Syst., 2020

2019

Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

2017

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2016

2015

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

An all-digital PWM generator with 62.5ps resolution in 28nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS.

[BibT_eX]

[DOI]

CoRR, 2014

A 10 bit 16 MS/s redundant SAR ADC with flexible window function for a digitally controlled DC-DC converter in 28 nm CMOS.

[BibT_eX]

[DOI]

Stefan Hänzsche

Sebastian Höppner

René Schüffny

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

A compact on-chip IR-drop measurement system in 28 nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Hybrid incremental-ΣΔ-ADC for ambient light sensing applications.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Rapid prototyping of higher order incremental ΣΔ-ADC topologies and NTFs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Electronics, 2013

Analysis of a charge redistribution SAR ADC with partially thermometer coded DAC.

[BibT_eX]

[DOI]

Stefan Hänzsche

René Schüffny

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Behavioral model of a continuous current integrator with time discrete feedback and sampling.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

A 32 GBit/s communication SoC for a waferscale neuromorphic system.

[BibT_eX]

[DOI]

Integr., 2012

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 14 bit self-calibrating charge redistribution SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Stefan Hänzsche

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