Stefan Gehrer

J. Cryptogr. Eng., 2020

Encoding Power Traces as Images for Efficient Side-Channel Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

Lightweight Side-Channel Protection using Dynamic Clock Randomization.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Deep Learning Multi-Channel Fusion Attack Against Side-Channel Protected Hardware.

[BibT_eX]

[DOI]

Daniel Fennes

Sebastien Leger

Jan Richter-Brockmann

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Deep Neural Network Attribution Methods for Leakage Analysis and Symmetric Key Recovery.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Securing Cryptographic Circuits by Exploiting Implementation Diversity and Partial Reconfiguration on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Profiled Power Analysis Attacks Using Convolutional Neural Networks with Domain Knowledge.

[BibT_eX]

[DOI]

Proceedings of the Selected Areas in Cryptography - SAC 2018, 2018

2016

Area-Efficient PUF-Based Key Generation on System-on-Chips with FPGAs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

2015

Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generation.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Aging effects on ring-oscillator-based physical unclonable functions on FPGAs.

[BibT_eX]

[DOI]

Sebastien Leger

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

2014

Reconfigurable PUFs for FPGA-based SoCs.

[BibT_eX]

[DOI]