Stavros Simoglou
Orcid: 0000-0003-0015-7510
According to our database1,
Stavros Simoglou
authored at least 10 papers
between 2018 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
2023
Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018