Stanley Schuster
According to our database1,
Stanley Schuster
authored at least 13 papers
between 2000 and 2009.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1990, "For contributions to high-performance static random access memory design.".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2009
IEEE J. Solid State Circuits, 2009
2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008
2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2005
2003
Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz.
IEEE J. Solid State Circuits, 2003
2002
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
2001
A circuit level implementation of an adaptive issue queue for power-aware microprocessors.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
2000
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000
IBM J. Res. Dev., 2000
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000