Stanley Chen
According to our database1,
Stanley Chen
authored at least 11 papers
between 1988 and 2021.
Collaborative distances:
Collaborative distances:
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Bibliography
2021
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.
IEEE J. Solid State Circuits, 2021
2020
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2018
A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017
6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2012
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
1988
Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications, 1988