Stanislaw J. Piestrak

EURASIP J. Adv. Signal Process., December, 2023

2018

Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2018

Correction to: Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1} (n Even).

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2018

2017

Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1} (n Even).

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2017

Design of residue generators with CLA/compressor trees and multi-bit EAC.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016

Design of a low-power RNS-enhanced arithmetic unit.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015

A note on RNS architectures for the implementation of the diagonal function.

[BibT_eX]

[DOI]

Inf. Process. Lett., 2015

Fault-tolerant implementation of direct FIR filters protected using residue codes.

[BibT_eX]

[DOI]

Proceedings of the Nordic Circuits and Systems Conference, 2015

Fault-aware configurable logic block for reliable reconfigurable FPGAs.

[BibT_eX]

[DOI]

B. Chagun Basha

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Design of Reverse Converters for the New RNS Moduli Set {2n+1, 2n-1, 2n, 2n-1+1} (n odd).

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design of Reverse Converters for General RNS Moduli Sets {2k, 2n-1, 2n+1, 2n+1-1} and {2k, 2n-1, 2n+1, 2n-1-1} (n even).

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design of the coarse-grained reconfigurable architecture DART with on-line error detection.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

Private reliability environments for efficient fault-tolerance in CGRAs.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2014

Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs.

[BibT_eX]

[DOI]

B. Chagun Basha

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013

Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor.

[BibT_eX]

[DOI]

Hung-Manh Pham

IEEE Trans. Computers, 2013

Implementation and evaluation of configuration scrubbing on CGRAs: A case study.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on System on Chip, 2013

Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Design of an RNS reverse converter for a new five-moduli special set.

[BibT_eX]

[DOI]

Krzysztof S. Berezowski

Janusz Biernat

Aviral Shrivastava

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

Fast and energy-efficient constant-coefficient FIR filters using residue number system.

[BibT_eX]

[DOI]

Krzysztof S. Berezowski

Janusz Biernat

Aviral Shrivastava

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Design of multi-residue generators using shared logic.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Error recovery technique for coarse-grained reconfigurable architectures.

[BibT_eX]

[DOI]

Muhammad Moazam Azeem

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication".

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2010

Design of a fault-tolerant coarse-grained.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Design of cost-efficient multipliers modulo 2a-1.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Design of parallel fault-secure encoders for systematic cyclic block transmission codes.

[BibT_eX]

[DOI]

Houssein Jaber

Microelectron. J., 2009

Exploiting residue number system for power-efficient digital signal processing in embedded processors.

[BibT_eX]

[DOI]

Rooju Chokshi

Krzysztof S. Berezowski

Aviral Shrivastava

Proceedings of the 2009 International Conference on Compilers, 2009

2007

Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes.

[BibT_eX]

[DOI]

Houssein Jaber

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006

Characterizing Laser-Induced Pulses in ICs: Methodology and Results.

[BibT_eX]

[DOI]

Damien Leroy

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2005

Modeling of Transients Caused by a Laser Attack on Smart Cards.

[BibT_eX]

[DOI]

Damien Leroy

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2003

Designing fault-secure parallel encoders for systematic linear error correcting codes.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2003

2002

Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2002

Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2002

Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001

On the Design of Self-Testing Checkers for Modified Berger Codes.

[BibT_eX]

[DOI]

Xrysovalantis Kavousianos

Dimitris Bakalis

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

1999

Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

Jerzy W. Greblicki

Proceedings of the Dependable Computing, 1999

1998

Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

VLSI implementation and complexity comparison of residue generators modulo 3.

[BibT_eX]

[DOI]

Fabrice Pedron

Proceedings of the 9th European Signal Processing Conference, 1998

Membership Test Logic for Delay-Insensitive Codes.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997

Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes.

[BibT_eX]

[DOI]

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996

Design of minimal-level PLA self-testing checkers for m-out-of-n codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1996

Design of Self-Testing Checkers for Borden Codes.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

Self-Checking Design in Eastern Europe.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1996

1995

Towards Totally Self-Checking Delay-Insensitive Systems.

[BibT_eX]

[DOI]

Takashi Nanya

Proceedings of the Digest of Papers: FTCS-25, 1995

Design of self-testing checkers for unidirectional error detecting codes.

[BibT_eX]

PhD thesis, 1995

1994

Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1994

Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993

The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1993

1991

Efficient Encoding? Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes.

[BibT_eX]

[DOI]

Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

Design of a Self-Testing Checker for Borden Code.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990

Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1990

The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

1987

Design of Fast Self-Testing Checkers for a Class of Berger Codes.

[BibT_eX]

[DOI]