Stacy Ho

According to our database¹, Stacy Ho authored at least 8 papers between 2014 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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2024

A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2019

A 20 kHz Bandwidth Resistive DAC with 135 dBA Dynamic Range and 125 dB THD.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016

Analog-digital partitioning and coupling in 3D-IC for RF applications.

[BibT_eX]

[DOI]

Anantha P. Chandrakasan

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS.

[BibT_eX]

[DOI]

Do-Yeon Yoon

Stacy Ho

Hae-Seung Lee

IEEE J. Solid State Circuits, 2015

A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW CT MASH ΔΣ modulator in 28nm CMOS.

[BibT_eX]

[DOI]

Do-Yeon Yoon

Stacy Ho

Hae-Seung Lee

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2014

Stacy Ho

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