Srivatsava Jandhyala
Orcid: 0000-0002-1497-7264
According to our database1,
Srivatsava Jandhyala
authored at least 12 papers
between 2008 and 2024.
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Bibliography
2024
>Optimization of CMOS compatible non-perovskite ferroelectric gate stack for designing low power Ferroelectric tunnel FETs.
Proceedings of the 28th International Symposium on VLSI Design and Test, 2024
2023
IEEE Trans. Instrum. Meas., 2023
2022
Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
2021
An All-CMOS Supply, Temperature and Process Invariant Hybrid Current Reference For Power Efficient IoT Applications.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021
2019
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2016
An Accurate All CMOS Bandgap Reference Voltage with Integrated Temperature Sensor for IoT Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
2015
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
2013
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013
2008
Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008