Srivatsan Parthasarathy

According to our database1, Srivatsan Parthasarathy authored at least 6 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023
Optimization of SCR for High-Speed Digital and RF Applications in 45-nm SOI CMOS Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2017
ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications.
Microelectron. Reliab., 2017

2015
ESD protection clamp with active feedback and mis-trigger immunity in 28nm CMOS process.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Design optimization of SiGe BiCMOS Silicon Controlled Rectifier for Charged Device Model (CDM) protection applications.
Microelectron. Reliab., 2014


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