Sriram R. Vangal
Orcid: 0000-0003-1548-9876
According to our database1,
Sriram R. Vangal
authored at least 31 papers
between 2002 and 2021.
Collaborative distances:
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Bibliography
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Session 12 Overview: Innovations in Low-Power and Secure IoT Technology Directions Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
Introduction to the Special Section on the 2019 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019
2018
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A Sub-cm<sup>3</sup> Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications.
IEEE J. Solid State Circuits, 2017
IEEE Des. Test, 2017
2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2014
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
2012
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012
2011
A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS.
IEEE J. Solid State Circuits, 2011
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
IEEE J. Solid State Circuits, 2011
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
IEEE J. Solid State Circuits, 2011
2010
Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies.
IEEE Des. Test Comput., 2010
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the Conference on High Performance Computing Networking, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Proceedings of the Multicore Processors and Systems, 2009
2008
IEEE J. Solid State Circuits, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
2003
IEEE J. Solid State Circuits, 2003
2002
IEEE J. Solid State Circuits, 2002