Sriram Govindarajan

According to our database, Sriram Govindarajan authored at least 13 papers between 1996 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2001

Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures.

V. Srinivasan, Sriram Govindarajan, Ranga Vemuri

IEEE Trans. Very Large Scale Integr. Syst., 2001

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis.

Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri

Formal Methods Syst. Des., 2001

Application Specific Macro Based Synthesis.

Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000

A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures.

Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints.

Preetham Lakshmikanthan, Sriram Govindarajan, Vinoo Srinivasan, Ranga Vemuri

Proceedings of the Parallel and Distributed Processing, 2000

Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS.

Sriram Govindarajan, Ranga Vemuri

Proceedings of the Field-Programmable Logic and Applications, 2000

Improving the Schedule Quality of Static-List Time-Constrained Scheduling.

Sriram Govindarajan, Ranga Vemuri

Proceedings of the 2000 Design, 2000

1999

An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications.

Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss

Proceedings of the 36th Conference on Design Automation, 1999

1998

An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures.

Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri

Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

An Effective Design System for Dynamically Reconfigurable Architectures.

Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997

Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms.

Sriram Govindarajan, Ranga Vemuri

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Cone-based clustering heuristic for list-scheduling algorithms.

Sriram Govindarajan, Ranga Vemuri

Proceedings of the European Design and Test Conference, 1997

1996

Rapid Prototyping of Reconfigurable Coprocessors.

Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996