Srinivasan Subramaniyan
Orcid: 0000-0002-5848-5667
According to our database1,
Srinivasan Subramaniyan
authored at least 7 papers
between 2020 and 2024.
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Bibliography
2024
Latency-Guaranteed Co-Location of Inference and Training for Reducing Data Center Expenses.
Proceedings of the 44th IEEE International Conference on Distributed Computing Systems, 2024
2023
Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders.
IEEE Des. Test, February, 2023
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
2022
A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures.
IEEE Commun. Surv. Tutorials, 2022
MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
2020
Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020