Srinivasa Vemuru

According to our database1, Srinivasa Vemuru authored at least 23 papers between 1993 and 2015.

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Bibliography

2015
Comparison of power system simulation tools with load flow study cases.
Proceedings of the IEEE International Conference on Electro/Information Technology, 2015

2014
Majority Logic Synthesis Based on Nauty Algorithm.
Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

FPGA interconnect modeling for lifetime failure detection.
Proceedings of the IEEE International Conference on Electro/Information Technology, 2014

Majority logic gate synthesis approaches for post-CMOS logic circuits: A review.
Proceedings of the IEEE International Conference on Electro/Information Technology, 2014

2013
A spiral learning approach to hardware description languages.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

System design: A novel, project-based course connecting the dots of the electrical engineering curriculum.
Proceedings of the IEEE Frontiers in Education Conference, 2013

Comparison of multilevel DC-DC converter topologies.
Proceedings of the IEEE International Conference on Electro-Information Technology , 2013

Small signal modeling of diode in a parallel module subjected to partial shading.
Proceedings of the IEEE International Conference on Electro-Information Technology , 2013

2012
Modeling impact of bypass diodes on photovoltaic cell performance under partial shading.
Proceedings of the 2012 IEEE International Conference on Electro/Information Technology, 2012

Efficient AFT implementation in FPGAs to detect potential electromigration failures.
Proceedings of the 2012 IEEE International Conference on Electro/Information Technology, 2012

2011
Modeling of Random Shading Effects in Solar Cells.
Proceedings of the 21st International Conference on Systems Engineering (ICSEng 2011), 2011

2010
Analysis and test of electromigration failures in FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Built-In Self-Test Circuit Optimization for Embedded Cores.
Proceedings of the 2010 International Conference on Computer Design, 2010

Quantum-Dot Cellular Automata Implementation of FPGA Configurable Logic Blocks.
Proceedings of the 2010 International Conference on Computer Design, 2010

2008
Subbus Control Line Impact on Effectiveness of Bus Encoding Schemes.
Proceedings of the 2008 International Conference on Computer Design, 2008

2007
Preface.
Integr., 2007

2006
Bus Encoding Scheme To Eliminate Unwanted Signal Transitions.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005
BIST for Embedded SRAMs in System on Chips.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

2004
A Bus Encoding Scheme to Reduce Power Consuming Signal Transitions.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
Simultaneous Switching Noise Estimation Including the Effects of the Driving Transistor Gate-Source Capacitance.
Proceedings of the International Conference on VLSI, 2003

Channel Routing with Crosstalk Consideration.
Proceedings of the International Conference on VLSI, 2003

1994
Scaling of serially-connected MOSFET chains.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993
Short-circuit Power Dissipation Formulae for CMOS Gates.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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