Srinivasa Banna

According to our database, Srinivasa Banna authored at least 5 papers between 2015 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2018

32GHz resonant-fin transistors in 14nm FinFET technology.

Bichoy Bahr, Yanbo He, Zoran Krivokapic, Srinivasa Banna, Dana Weinstein

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016

On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs.

Jiajun Shi, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Csaba Andras Moritz

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions.

Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs.

Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Scaling challenges of FinFET technology at advanced nodes and its impact on SoC design (Invited).

Srinivasa Banna

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015