Srinivas Boppu

Orcid: 0000-0001-9028-2563

According to our database1, Srinivas Boppu authored at least 28 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Automating functional unit and register binding for synchoros CGRA platform.
Des. Autom. Embed. Syst., June, 2024

Resource-Efficient Derivative PPG-Based Signal Quality Assessment Using One-Dimensional CNN With Optimal Hyperparameters for Quality-Aware PPG Analysis.
IEEE Access, 2024

Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study.
IEEE Access, 2024

Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework.
IEEE Access, 2024

2023
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction.
ACM Trans. Design Autom. Electr. Syst., 2023

DRRA-based Reconfigurable Architecture for Mixed-Radix FFT.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Implementation of Image Averaging on DRRA and DiMArch Architectures.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures.
Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023

Compressive Sensing-Based Automatic PPG Signal Quality Assessment Using CNN for Energy-Constrained Medical Devices.
Proceedings of the 15th International Conference on Electronics, 2023

Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey.
IEEE Access, 2022

Efficient Hardware Architecture for Posit Addition/Subtraction.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Hand Gesture Recognition System in the Complex Background for Edge Computing Devices.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Efficient Multiplication and Accumulation of Signed Numbers.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021
Design and Implementation of Optimized Register File for Streaming Applications.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2020
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

An Automated Algorithm for Estimating Respiration Rate from PPG Signals.
Proceedings of the Machine Learning, Image Processing, Network Security and Data Sciences, 2020

2019
Design of a Real-Time Automatic Source Monitoring Framework Based on Sound Source Localization.
Proceedings of the 7th International Conference on Digital Information Processing and Communications, 2019

2015
Code Generation for Tightly Coupled Processor Arrays.
PhD thesis, 2015

2014
Compact Code Generation for Tightly-Coupled Processor Arrays.
J. Signal Process. Syst., 2014

Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach.
ACM Trans. Embed. Comput. Syst., 2014

2013
System integration of tightly-coupled processor arrays using reconfigurable buffer structures.
Proceedings of the Computing Frontiers Conference, 2013

Loop program mapping and compact code generation for programmable hardware accelerators.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Hierarchical power management for adaptive tightly-coupled processor arrays.
ACM Trans. Design Autom. Electr. Syst., 2012

A prototype of an invasive tightly-coupled processor array.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Design of Low Power On-chip Processor Arrays.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011


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