Srini Devadas

IEEE Trans. Very Large Scale Integr. Syst., 2002

Proxy-based security protocols in networked mobile devices.

[BibT_eX]

[DOI]

Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), 2002

The Untrusted Computer Problem and Camera-Based Authentication.

[BibT_eX]

[DOI]

Proceedings of the Pervasive Computing, 2002

A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning.

[BibT_eX]

[DOI]

G. Edward Suh

Larry Rudolph

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Silicon physical random functions.

[BibT_eX]

[DOI]

Proceedings of the 9th ACM Conference on Computer and Communications Security, 2002

Controlled Physical Random Functions.

[BibT_eX]

[DOI]

Proceedings of the 18th Annual Computer Security Applications Conference (ACSAC 2002), 2002

2001

OCCOM-efficient computation of observability-based code coveragemetrics for functional verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Functional vector generation for HDL models using linearprogramming and Boolean satisfiability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Effects of Memory Performance on Parallel Job Scheduling.

[BibT_eX]

[DOI]

G. Edward Suh

Larry Rudolph

Proceedings of the Job Scheduling Strategies for Parallel Processing, 2001

Analytical cache models with applications to cache partitioning.

[BibT_eX]

[DOI]

G. Edward Suh

Larry Rudolph

Proceedings of the 15th international conference on Supercomputing, 2001

Software-Assisted Cache Replacement Mechanisms for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

Solving covering problems using LPR-based lower bounds.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

ISDL: An Instruction Set Description Language for Retargetability and Architecture Exploration.

[BibT_eX]

[DOI]

Silvina Hanono

Des. Autom. Embed. Syst., 2000

A New Approach to Solving the Hardware-Software Partitioning Problem in Embedded System Design.

[BibT_eX]

[DOI]

Daniel W. Engels

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Observability Analysis of Embedded Software for Coverage-Directed Validation.

[BibT_eX]

[DOI]

José C. Costa

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Application-specific memory management for embedded systems using software-controlled caches.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

A text-compression-based method for code size minimization in embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1999

Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures.

[BibT_eX]

[DOI]

Ashok Sudarsanam

Des. Autom. Embed. Syst., 1999

CAD Techniques for Embedded System Design.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Automatic architecture evaluation for hardware/software codesign.

[BibT_eX]

[DOI]

Pietro Russo

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A probabilistic approach for RT-level power modeling.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A Methodology for Accurate Performance Evaluation in Architecture Exploration.

[BibT_eX]

[DOI]

Pietro Russo

Proceedings of the 36th Conference on Design Automation, 1999

Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

A low power, low bandwidth protocol for remote wireless terminals.

[BibT_eX]

[DOI]

Anantha P. Chandrakasan

Wirel. Networks, 1998

A new viewpoint on code generation for directed acyclic graphs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1998

BDD-based synthesis of extended burst-mode controllers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Sequential logic optimization for low power using input-disabling precomputation architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Code density optimization for embedded DSP processors using data compression techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Power Estimation Under User-Specified Input Sequences and Programs.

[BibT_eX]

[DOI]

Integr. Comput. Aided Eng., 1998

Code Optimization Techniques in Embedded DSP Microprocessors.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 1998

An algorithmic approach to optimizing fault coverage for BIST logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator.

[BibT_eX]

[DOI]

Silvina Hanono

Proceedings of the 35th Conference on Design Automation, 1998

OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

1997

Estimation of average switching activity in combinational logic circuits using symbolic simulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Switching activity estimation using limited depth reconvergent path analysis.

[BibT_eX]

[DOI]

José C. Costa

José C. Monteiro

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Solving Covering Problems Using LPR-Based Lower Bounds.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

ISDL: An Instruction Set Description Language for Retargetability.

[BibT_eX]

[DOI]

Silvina Hanono

Proceedings of the 34st Conference on Design Automation, 1997

1996

Techniques for power estimation and optimization at the logic level: A survey.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1996

Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1996

Storage Assignment to Decrease Code Size.

[BibT_eX]

[DOI]

ACM Trans. Program. Lang. Syst., 1996

Addendum to "Synthesis of robust delay-fault testable circuits: Theory".

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

An observability-based code coverage metric for functional simulation.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Scheduling Techniques to Enable Power Management.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Power estimation methods for sequential logic circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1995

Probabilistic manipulation of Boolean functions using free Boolean diagrams.

[BibT_eX]

[DOI]

Amelia Shen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams.

[BibT_eX]

[DOI]

Bill Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Instruction selection using binate covering for code size optimization.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A Survey of Optimization Techniques Targeting Low Power VLSI Circuits.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

Optimization of combinational and sequential logic circuits for low power using precomputation.

[BibT_eX]

[DOI]

Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994

Verification of asynchronous interface circuits with bounded wire delays.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1994

Certified timing verification and the transition delay of a logic circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

Precomputation-based sequential logic optimization for low power.

[BibT_eX]

[DOI]

Marios C. Papaefthymiou

IEEE Trans. Very Large Scale Integr. Syst., 1994

Event suppression: improving the efficiency of timing simulation for synchronous digital circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs.

[BibT_eX]

[DOI]

Filip Van Aelten

Jonathan Allen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Bitwise Encoding of Finite State Machines.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

Performance-driven synthesis of asynchronous controllers.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams.

[BibT_eX]

[DOI]

Bill Lin

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Challenges in code generation for embedded processors.

[BibT_eX]

Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits.

[BibT_eX]

[DOI]

Bill Lin

Proceedings of the 31st Conference on Design Automation, 1994

Automatic Verification of Pipelined Microprocessors.

[BibT_eX]

[DOI]

Vishal Bhagwati

Proceedings of the 31st Conference on Design Automation, 1994

1993

Analysis and Design of Regular Structures for Robust Dynamic Fault Testability.

[BibT_eX]

[DOI]

Michael J. Bryan

VLSI Design, 1993

Statistical timing analysis of combinational logic circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1993

Sequential test generation and synthesis for testability at the register-transfer and logic levels.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Computation of floating mode delay in combinational circuits: practice and implementation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Computation of floating mode delay in combinational circuits: theory and algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Comparing two-level and ordered binary decision diagram representations of logic functions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Delay-fault test generation and synthesis for testability under a standard scan design methodology.

[BibT_eX]

[DOI]

Kwang-Ting Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Verification of relations between synchronous machines.

[BibT_eX]

[DOI]

Filip Van Aelten

Jonathan Allen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Path-delay-fault testability properties of multiplexor-based networks.

[BibT_eX]

[DOI]

Integr., 1993

Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1993

Guest editorial.

[BibT_eX]

[DOI]

Petra Michel

J. Electron. Test., 1993

A synthesis-based test generation and compaction algorithm for multifaults.

[BibT_eX]

[DOI]

J. Electron. Test., 1993

Probabilistic construction and manipulation of free Boolean diagrams.

[BibT_eX]

[DOI]

Amelia Shen

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Retiming sequential circuits for low power.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Boolean factorization using multiple-valued minimization.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

Heuristic minimization of Boolean relations using testing techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation.

[BibT_eX]

[DOI]

Jacob K. White

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Validatable nonrobust delay-fault testable circuits via logic synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Synthesis of robust delay-fault-testable circuits: practice.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Synthesis of robust delay-fault-testable circuits: theory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks.

[BibT_eX]

[DOI]

Michael J. Bryan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Boolean satisfiability and equivalence checking using general Binary Decision Diagrams.

[BibT_eX]

[DOI]

Integr., 1992

Statistical Timing Analysis of Combinational Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

On average power dissipation and random pattern testability of CMOS combinational logic networks.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Automatic generation and verification of sufficient correctness properties for synchronous processors.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Estimation of Average Switching Activity in Combinational and Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

Test generation and verification for highly sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Exact algorithms for output encoding, state assignment, and four-level Boolean minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A unified approach to the synthesis of fully testable sequential machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Optimizing interacting finite state machines using sequential don't cares.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Irredundant interacting sequential machines via optimal logic synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Optimum and heuristic algorithms for an approach to finite state machine decomposition.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

An automata-theoretic approach to behavioral equivalence.

[BibT_eX]

[DOI]

Integr., 1991

Recent progress in synthesis for testability.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits.

[BibT_eX]

[DOI]

Kwang-Ting Cheng

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Design Verfication and Reachability Analysis Using Algebraic Manipulation.

[BibT_eX]

[DOI]

A. S. Krishnakumar

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Finite State Machine Decomposition by Transition Pairing.

[BibT_eX]

[DOI]

James H. Kukula

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Delay Computation in Combinational Logic Circuits: Theory and Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology.

[BibT_eX]

[DOI]

Kwang-Ting Cheng

Proceedings of the 28th Design Automation Conference, 1991

1990

Irredundant sequential machines via optimal logic synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Easily testable PLA-based finite state machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Redundancies and don't cares in sequential logic synthesis.

[BibT_eX]

[DOI]

J. Electron. Test., 1990

Sequential logic synthesis for testability using register-transfer level descriptions.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Design of integrated circuits fully testable for delay-faults and multifaults.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Minimization of Functions with Multiple-Valued Outputs: Theory and Applications.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

Testability driven synthesis of interacting finite state machines.

[BibT_eX]

[DOI]

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Testability-Preserving Circuit Transformations.

[BibT_eX]

[DOI]

Michael J. Bryan

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Sequential Test Generation at the Register-Transfer and Logic Levels.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Verification of Interacting Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Boolean decomposition in multilevel logic optimization.

[BibT_eX]

[DOI]

Albert R. Wang

IEEE J. Solid State Circuits, April, 1989

Logic verification algorithms and their parallel implementation.

[BibT_eX]

[DOI]

Ruey-Sing Wei

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Decomposition and factorization of sequential finite state machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Algorithms for hardware allocation in data path synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

A synthesis and optimization procedure for fully and easily testable sequential machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Delay Test Generation for Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1989, 1989

Test generation for highly sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Boolean minimization and algebraic factorization procedures for fully testable sequential machines.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Optimal layout via Boolean satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Optimum and heuristic algorithms for finite state machine decomposition and partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Easily testable PLA-based finite state machines.

[BibT_eX]

[DOI]

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

General Decomposition of Sequential Machines: Relationships to State Assignment.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Approaches to Multi-level Sequential Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Test generation for sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

On the verification of sequential machines at differing levels of abstraction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Techniques for multilayer channel routing.

[BibT_eX]

[DOI]

Douglas Braun

Jeffrey L. Burns

Fabio Romeo

Kartikeya Mayaram

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

An Incomplete Scan Design Approach to Test Generation for Sequential Machines.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1988, 1988

Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1988, 1988

Boolean decomposition in multi-level logic optimization.

[BibT_eX]

[DOI]

Albert R. Wang

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

Topological Optimization of Multiple-Level Array Logic.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1986

GENIE: a generalized array optimizer for VLSI synthesis.

[BibT_eX]

[DOI]

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

Chameleon: a new multi-layer channel router.

[BibT_eX]

[DOI]