Srinath R. Naidu

According to our database, Srinath R. Naidu authored at least 11 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Optimal oversampling ratio in two-step simulation.

Srinath R. Naidu, Gopalakrishnan Venkiteswaran

Monte Carlo Methods Appl., 2024

2018

Fast Approach for Iris Detection on GPU by Applying Search Localization for Circular Hough Transform.

Pinkey Kumari, Srinath R. Naidu

Proceedings of the 2018 International Conference on Advances in Computing, 2018

2016

Accelerated evolutionary algorithms with parameterimportance based population initialization for variation-aware analog yield optimization.

Sita Kondamadugula, Srinath R. Naidu

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Parameter-importance based Monte-Carlo Technique for Variation-aware Analog Yield Optimization.

Sita Kondamadugula, Srinath R. Naidu

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Geometric Programming Formulation for Gate Sizing with Pipelining Constraints.

Srinath R. Naidu

Proceedings of the 28th International Conference on VLSI Design, 2015

2007

Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits.

Srinath R. Naidu

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Use of statistical timing analysis on real designs.

A. Nardi, Emre Tuncer, Srinath R. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits.

Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2003

On Synthesis of Easily Testable (k, K) Circuits.

Srinath R. Naidu, Vijay Chandru

IEEE Trans. Computers, 2003

2002

Timing Yield Calculation Using an Impulse-Train Approach.

Srinath R. Naidu

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

Minimizing stand-by leakage power in static CMOS circuits.

Srinath R. Naidu, E. T. A. F. Jacobs

Proceedings of the Conference on Design, Automation and Test in Europe, 2001