Srikanth T. Srinivasan

According to our database1, Srikanth T. Srinivasan authored at least 14 papers between 1999 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2009
Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2007
Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2006
Scalable Load and Store Processing in Latency-Tolerant Processors.
IEEE Micro, 2006

2004
An analysis of a resource efficient checkpoint architecture.
ACM Trans. Archit. Code Optim., 2004

Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance.
IEEE Micro, 2004

A Minimal Dual-Core Speculative Multi-Threading Architecture.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Reducing Branch Misprediction Penalty via Selective Branch Recovery.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Perceptron-Based Branch Confidence Estimation.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Continual flow pipelines.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2003
Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers.
IEEE Micro, 2003

Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Recycling waste: exploiting wrong-path execution to improve branch prediction.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

2001
Locality vs. criticality.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

1999
Load Latency Tolerance in Dynamically Scheduled Processors.
J. Instr. Level Parallelism, 1999


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