Srikanth Arekapudi

According to our database1, Srikanth Arekapudi authored at least 12 papers between 2001 and 2016.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
Carrizo: A High Performance, Energy Efficient 28 nm APU.
IEEE J. Solid State Circuits, 2016

2013
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor.
IEEE J. Solid State Circuits, 2013

2012
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS.
IEEE J. Solid State Circuits, 2012

2011
40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2006
A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Using Hardware to Configure a Load-Balanced Switch.
IEEE Micro, 2005

A low-power distributed wide-band LNA in 0.18µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Configuring a load-balanced switch in hardware.
Proceedings of the 12th Annual IEEE Symposium on High Performance Interconnects, 2004

2003
ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems.
J. Circuits Syst. Comput., 2003

2002
ATPG for timing-induced functional errors on trigger events in hardware-software systems.
Proceedings of the 7th European Test Workshop, 2002

2001
Test pattern generation for timing-induced functional errors in hardware-software systems.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001


  Loading...