Sri Navaneeth Easwaran
Orcid: 0000-0001-5167-1056
According to our database1,
Sri Navaneeth Easwaran
authored at least 8 papers
between 2017 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
Configurable and Scalable High-Side or Low-Side Driver in BiCMOS with 20dBµV Emission at 88MHz.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2020
2019
3A Fault Tolerant Low Side Driver Circuit Design Using Design FMEA for Automotive Applications.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Portable and Scalable High Voltage Circuits for Automotive Applications in BiCMOS Processes.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
Voltage and Current Selector-Based Biasing Topology for Multiple Supply Voltage Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
1.3A, -2V Tolerant Solenoid Drivers for Pedestrian Protection in Active Hood Lift Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
40V High Side PSI5 Transceiver with 65dBµV Conducted Emission Level in a BiCMOS Process.
Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018
2017
Thermal simulation aided 98mJ integrated high side and low side drivers design for safety SOCs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
100mV precision 40V tolerant scalable cap free current limited voltage source for wide input current range.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017