Sreeranga P. Rajan
According to our database1,
Sreeranga P. Rajan
authored at least 35 papers
between 1992 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2022
A contextual multi-task neural approach to medication and adverse events identification from clinical text.
J. Biomed. Informatics, 2022
2021
Unified concept and assertion detection using contextual multi-task learning in a clinical decision support system.
J. Biomed. Informatics, 2021
2020
Evaluation of Transfer Learning for Adverse Drug Event (ADE) and Medication Entity Extraction.
Proceedings of the 3rd Clinical Natural Language Processing Workshop, 2020
2018
Proceedings of the 2018 International Conference on Advances in Computing, 2018
2017
IEEE Softw., 2017
2014
Proceedings of the Intelligent Distributed Computing, 2014
2013
2012
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012
2011
Proceedings of the Software and Data Technologies - 6th International Conference, 2011
Client-tier Validation of Dynamic Web Applications.
Proceedings of the ICSOFT 2011, 2011
Proceedings of the Fundamental Approaches to Software Engineering, 2011
Proceedings of the Computer Aided Verification - 23rd International Conference, 2011
2009
Proceedings of the 31st International Conference on Software Engineering, 2009
2008
Proceedings of the Programming Languages and Systems, 6th Asian Symposium, 2008
2007
Proceedings of the 22nd IEEE/ACM International Conference on Automated Software Engineering (ASE 2007), 2007
2006
Int. J. Parallel Program., 2006
Proceedings of the ACM/SIGSOFT International Symposium on Software Testing and Analysis, 2006
2005
Proceedings of the 3rd Workshop on Software Model Checking, 2005
2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
2002
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
2000
Proceedings of the 37th Conference on Design Automation, 2000
1999
Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999
Proceedings of the Correct Hardware Design and Verification Methods, 1999
Proceedings of the Computer Aided Verification, 11th International Conference, 1999
1998
ATM switch design by high-level modeling, formal verification and high-level synthesis.
ACM Trans. Design Autom. Electr. Syst., 1998
Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol.
Proceedings of the Applied Formal Methods, 1998
1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the Algebraic Methodology and Software Technology, 1997
1996
ACM Trans. Design Autom. Electr. Syst., 1996
1993
From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993
1992
Executing HOL Specifications: Towards an Evaluation Semantics for Classical Higher Order Logic.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1992