Sreehari Veeramachaneni

Orcid: 0000-0001-7744-4580

According to our database1, Sreehari Veeramachaneni authored at least 48 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor.
IEEE Embed. Syst. Lett., June, 2024

ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks.
IEEE Access, 2024

Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Bistable Physically Unclonable Function with Dynamic Threshold Voltage.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Energy-Efficient Ternary Multiplier.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs.
Integr., November, 2023

Optimized Fault-Tolerant Adder Design Using Error Analysis.
J. Circuits Syst. Comput., April, 2023

Power Efficient Approximate Ternary Subtractor for Image Processing Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Design of Energy Efficient Posit Multiplier.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Hardware efficient circuit for low error logarithmic converter.
J. Comput. Methods Sci. Eng., 2022

A New Approximate 4-2 Compressor using Merged Sum and Carry.
J. Electron. Test., 2022

A Low Error, Hardware Efficient Logarithmic Multiplier.
Circuits Syst. Signal Process., 2022

Logic Locking Designs at Transistor Level for Full Adders.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021
A low-error, memory-based fast binary antilogarithmic converter.
Int. J. Circuit Theory Appl., 2021

Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication.
IET Comput. Digit. Tech., 2021

Energy efficient signed and unsigned radix 16 booth multiplier design.
Comput. Electr. Eng., 2021

Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Design and Analysis of Obfuscated Full Adders.
Proceedings of the International Conference on Microelectronics, 2021

Energy Efficient Approximate 4: 2 Compressors for Error Tolerant Applications.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
Efficient implementation of mixed-precision multiply-accumulator unit for AI algorithms.
Int. J. Circuit Theory Appl., 2020

2018
An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2014
A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

An Optimized Design of Reversible Quantum Comparator.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A New Design of an N-Bit Reversible Arithmetic Logic Unit.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2012
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.
Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Prefix-Based Optimal Reversible Comparator.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A Modified Twin Precision Multiplier with 2D Bypassing Technique.
Proceedings of the International Symposium on Electronic System Design, 2012

CNFET based ternary magnitude comparator.
Proceedings of the International Symposium on Communications and Information Technologies, 2012

2011
A Prefix Based Reconfigurable Adder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.
Proceedings of the International Symposium on Electronic System Design, 2011

A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter.
Proceedings of the International Symposium on Electronic System Design, 2011

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.
Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

A Unified Architecture for BCD and Binary Adder/Subtractor.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
J. Low Power Electron., 2010

An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A low power, variable resolution two-step flash ADC.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Low power, variable resolution pipelined analog to Digital converter with sub flash architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter.
J. Low Power Electron., 2009

Design of a Low Power, Variable-Resolution Flash ADC.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A novel low power, variable resolution pipelined ADC.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A High Performance Unified BCD and Binary Adder/Subtractor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Novel High-Speed Redundant Binary to Binary converter using Prefix Networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Novel architectures for efficient (m, n) parallel counters.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007


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