Sreedhar Natarajan

According to our database1, Sreedhar Natarajan authored at least 23 papers between 2002 and 2014.

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Bibliography

2014
13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Semantic Information Modeling for Emerging Applications in Smart Grid.
Proceedings of the Ninth International Conference on Information Technology: New Generations, 2012

2011
Toward data-driven demand-response optimization in a campus microgrid.
Proceedings of the BuildSys 2011, 2011

2008
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2008

A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Private Equity: Fight them or Invite them.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
E1 Ultimate Limits of Integrated Electronics.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2006

2005
Impact of negative bias temperature instability on digital circuit reliability.
Microelectron. Reliab., 2005

Introduction to the Special Issue on the IEEE 2004 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2005

Introduction to the Special Issue on the ISSCC2004.
IEEE J. Solid State Circuits, 2005

2004
A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process.
IEEE J. Solid State Circuits, 2004

Introduction to the Special Issue on the IEEE 2003 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2004

Leakage Reduction techniques in a 0.13um SRAM Cell.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A high density, low leakage, 5T SRAM for embedded caches.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2002
Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

SOI SRAM design advances & considerations.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

PD-SOI and FD-SOI: a comparison of circuit performance.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002


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