Spyros Stathopoulos

Orcid: 0000-0002-0833-6209

According to our database1, Spyros Stathopoulos authored at least 22 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2023
Text classification in memristor-based spiking neural networks.
Neuromorph. Comput. Eng., March, 2023

Fault Pruning: Robust Training of Neural Networks with Memristive Weights.
Proceedings of the Unconventional Computation and Natural Computation, 2023

Tone Stimulus Detection For Rats Using RRAM-Based Local Field Potential Monitoring.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

2022
Multi-State Memristors and Their Applications: An Overview.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

NeuroPack: An Algorithm-level Python-based Simulator for Memristor-empowered Neuro-inspired Computing.
CoRR, 2022

An Absorbing Markov Chain Model for Stochastic Memristive Devices.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

A CMOS-based Characterisation Platform for Emerging RRAM Technologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A tool for emulating neuromorphic architectures with memristive models and devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Emulating homoeostatic effects with metal-oxide memristors T-dependence.
CoRR, 2021

Palimpsest Memories Stored in Memristive Synapses.
CoRR, 2021

A Stochastic Compact Model Describing Memristor Plasticity and Volatility.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
Hybrid CMOS/Memristor Circuit Design Methodology.
CoRR, 2020

A Reconfigurable CMOS-Memristor Active Inductor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018
A Data-Driven Verilog-A ReRAM Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Benchmarking Analogue Performance of Emerging Random Access Memory Technologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Live Demonstration: Benchmarking Analogue Performance of Emerging Random Access Memory Technologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Metal Oxide-enabled Reconfigurable Memristive Threshold Logic Gates.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Embedded Environmental Control Micro-chamber System for RRAM Memristor Characterisation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Live Demonstration: An Embedded Environmental Control Micro-chamber System for RRAM Memristor Characterisation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Live demonstration: A TiO2 ReRAM parameter extraction method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017


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