Spencer K. Millican
Orcid: 0000-0003-3682-4610
According to our database1,
Spencer K. Millican
authored at least 24 papers
between 2012 and 2024.
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Bibliography
2024
J. Electron. Test., April, 2024
2022
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion.
J. Electron. Test., 2022
2021
Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
Simulating and Evaluating a Quaternary Logic FPGA Based on Floating-gate Memories and Voltage Division.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
A study of transistor degradation in cyber-physical system control devices: work-in-progress.
Proceedings of the CODES/ISSS 2021, 2021
2020
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures.
J. Electron. Test., 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Calculating Signal Controllability using Neural Networks: Improvements to Testability Analysis and Test Point Insertion.
Proceedings of the 29th IEEE North Atlantic Test Workshop, 2020
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the 28th IEEE North Atlantic Test Workshop, 2019
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2015
Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints.
Proceedings of the 28th International Conference on VLSI Design, 2015
2014
Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling.
J. Electron. Test., 2014
A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
2013
Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits.
Proceedings of the 21st IEEE Asian Test Symposium, 2012