Spandana Rachamalla

According to our database, Spandana Rachamalla authored at least 6 papers between 2015 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Heterogeneity aware power abstractions for dynamic power dominated FinFET-based microprocessors.

Spandana Rachamalla, Shashidhar Reddy, Arun Joseph

IET Comput. Digit. Tech., 2019

Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis.

Arun Joseph, Spandana Rachamalla, Shashidhar Reddy, Nagu R. Dhanwada

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2016

FVCAG: A framework for formal verification driven power modeling and verification.

Arun Joseph, Spandana Rachamalla, Rahul M. Rao, Anand Haridass, Pradeep Kumar Nalla

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

2015

FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by Firmware.

Arun Joseph, Anand Haridass, Charles Lefurgy, Spandana Rachamalla, Sreekanth Pai, Diyanesh Chinnakkonda, Vidushi Goyal

Proceedings of the 28th International Conference on VLSI Design, 2015

Virtual logic netlist: Enabling efficient RTL analysis.

Spandana Rachamalla, Arun Joseph, Rahul M. Rao, Diwesh Pandey

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

FreqLeak: A frequency step based method for efficient leakage power characterization in a system.

Arun Joseph, Anand Haridass, Charles Lefurgy, Sreekanth Pai, Spandana Rachamalla, Francesco Campisano

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015