Soyeong Shin
Orcid: 0000-0002-6439-4825
According to our database1,
Soyeong Shin
authored at least 11 papers
between 2017 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration.
IEEE J. Solid State Circuits, 2021
2020
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 370-fJ/b, 0.0056 mm<sup>2</sup>/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2017
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017