Sourajeet Roy
Orcid: 0000-0002-9860-3242
According to our database1,
Sourajeet Roy
authored at least 10 papers
between 2009 and 2023.
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Bibliography
2023
Fast Multi-ANN Composite Models for Repeater Optimization in Presence of Parametric Uncertainty for on-Chip Hybrid Copper-Graphene Interconnects.
IEEE Access, 2023
2022
A Bilevel Multi-Fidelity Polynomial Chaos Approach for the Uncertainty Quantification of MWCNT Interconnect Networks With Variable Imperfect Contact Resistances.
IEEE Access, 2022
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs.
Proceedings of the Device Research Conference, 2022
2020
Statistical Analysis of Temperature Variability on the Write Efficiency of Spin-Orbit Torque MRAM using Polynomial Chaos Metamodels.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
2017
IEEE Access, 2017
2016
Sparse Linear Regression (SPLINER) Approach for Efficient Multidimensional Uncertainty Quantification of High-Speed Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
2011
Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Transient Simulation of Distributed Networks Using Delay Extraction Based Numerical Convolution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
2009
Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects Using a Matrix Rational Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009