Sounil Biswas

According to our database1, Sounil Biswas authored at least 12 papers between 2003 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
SERDES external loopback test using production parametric-test hardware.
Proceedings of the 2016 IEEE International Test Conference, 2016

2014
Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis.
ACM Trans. Design Autom. Electr. Syst., 2014

Innovative practices session 5C: Machine learning and data analysis in test.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

2012
An Industrial Study of System-Level Test.
IEEE Des. Test Comput., 2012

2011
Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2009
Maintaining Accuracy of Test Compaction through Adaptive Re-learning.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008
Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Improving the Accuracy of Test Compaction through Adaptive Test Update.
Proceedings of the 2008 IEEE International Test Conference, 2008

2006
Statistical Test Compaction Using Binary Decision Trees.
IEEE Des. Test Comput., 2006

2005
Specification Test Compaction for Analog Circuits and MEMS.
Proceedings of the 2005 Design, 2005

2004
Generalized Sensitization using Fault Tuples.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

2003
A Path Sensitization Technique for Testing of Switched Capacitor Circuits.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003


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