Sounak Roy

Orcid: 0000-0001-6361-6871

According to our database1, Sounak Roy authored at least 13 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A low power offset voltage calibration method for flash ADCs.
Integr., 2023

2022
A Self-Calibration Method of a Pipeline ADC Based on Dynamic Capacitance Allotment.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A digitally controlled adaptive LDO for power management unit in sensor node.
Integr., 2022

2021
A Square Wave-Based Digital Foreground Calibration Algorithm of a Pipeline ADC Using Approximate Harmonic Sampling.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Fully Digital Foreground Calibration Technique of A Flash ADC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020
An Adaptive Digitally Tuned Flash-based LDO with Reduced Hardware for Sensor Nodes in WBAN.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A Fast Transient Digitally Assisted Flash-Based Modular LDO for Sensor Nodes in WBAN.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019
Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

A Low Power mixed Signal Foreground Calibration Technique of a Pipeline ADC using a Variable Gain Amplifier.
Proceedings of the TENCON 2019, 2019

2018
Sinusoid Based Foreground Calibration Algorithm of a Pipeline ADC Using Time Averaged Radix Extraction.
Proceedings of the TENCON 2018, 2018

2013
Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC).
Microelectron. J., 2013

2012
Radix based digital calibration technique for pipelined ADC using Nyquist sampling of sinusoid.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2008
A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008


  Loading...