Soumya Pandit

According to our database, Soumya Pandit authored at least 16 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Design of FPGA based Custom IP Core to Detect the Edges of Brain Tumors.

Soumita Chatterjee, Soumya Pandit, Arpita Das

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

Design of A Custom IP Core for Concatenated SVM Model to Classify Multi-class Handwritten Numerical Characters.

Shraman Biswas, Soumya Pandit, Arpita Das

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

2022

Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect.

Subrata Das, Debesh Kumar Das, Soumya Pandit

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021

Minimization of Switching Activity of Graphene Based Circuits.

Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2020

A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects.

Subrata Das, Debesh Kumar Das, Soumya Pandit

ACM J. Emerg. Technol. Comput. Syst., 2020

2019

FPGA Based Hardware Design for Noise Suppression and Seismic Event Detection.

Samik Basu, Soumya Pandit, Amlan Chakrabarti, Soma Barman Mandal

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2014

Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications.

Debayan Bairagi, Soumya Pandit

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2013

An Improved <i>g</i> _<i>m</i>/<i>I</i> _<i>D</i> Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design.

Somnath Paul, Abhijit Dana, Soumya Pandit

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2012

Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics.

Joyjit Mukhopadhyay, Soumya Pandit

VLSI Design, 2012

2011

A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies.

Soumya Pandit, Chittaranjan A. Mandal, Amit Patra

VLSI Design, 2011

Statistical Simulation and Modeling of Nano-scale CMOS VCO Using Artificial Neural Network.

Sipra Mandal, Soumya Pandit

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2010

An automated high-level topology generation procedure for continuous-time SigmaDelta modulator.

Soumya Pandit, Chittaranjan A. Mandal, Amit Patra

Integr., 2010

2009

Systematic Methodology for High-Level Performance Modeling of Analog Systems.

Soumya Pandit, Chittaranjan A. Mandal, Amit Patra

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

A Fast Exploration Procedure for Analog High-Level Specification Translation.

Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2006

A formal approach for high level synthesis of linear analog systems.

Soumya Pandit, Chittaranjan A. Mandal, Amit Patra

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count.

Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra

Proceedings of the Conference on Design, Automation and Test in Europe, 2006