Soumya J.

According to our database, Soumya J. authored at least 49 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

FGG: Feedback Guided Generation to Accelerate Functional Coverage Closure on Network-on-Chip Processors.

N. Vamshi Krishna, Anushka Chaudhary, Soumya J.

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA.

Mekala Bindu Bhargavi, Sai Siddharth Rokkam, Sri Parameswaran, Soumya J.

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

Optimizing LU Decomposition with RISC-V Based Hardware Acceleration.

Mekala Bindu Bhargavi, Grandhala Sri Sai Harshith, Sri Parameswaran, Soumya J.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023

Improving the Functional Coverage Closure of Network-on-Chip using Particle Swarm Optimization.

N. Vamshi Krishna, Aruna, Soumya J.

Proceedings of the 19th International Conference on Synthesis, 2023

Improving Functional Coverage of Network-On-Chip Using Differential Evolution.

N. Vamshi Krishna, Rahul Tripathy, Joshitha Marripudi, Soumya J.

Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

Improving the Functional Coverage Closure of Network-on-Chip using Genetic Algorithm.

N. Vamshi Krishna, Jay P. Shah, Soumya J.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

NoC Application Mapping Optimization Using Reinforcement Learning.

Jagadheesh Samala, P. Veda Bhanu, Soumya J.

ACM Trans. Design Autom. Electr. Syst., 2022

Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation.

Jagadheesh Samala, P. Veda Bhanu, Soumya J., Linga Reddy Cenkeramaddi

IEEE Access, 2022

Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework.

M. K. Aparna Nair, Police Manoj Kumar Reddy, Y. L. Abijith, Venkatesh Rajagopalan, Soumya J.

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANN.

Jitesh Choudhary, Vishesh Bindal, Soumya J.

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021

Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip.

P. Veda Bhanu, Soumya J.

J. Syst. Archit., 2021

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA.

P. Veda Bhanu, Rahul Govindan, Rajat Kumar, Vishal Singh, Soumya J., Linga Reddy Cenkeramaddi

IEEE Access, 2021

Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA.

P. Veda Bhanu, Rahul Govindan, Plava Kattamuri, Soumya J., Linga Reddy Cenkeramaddi

IEEE Access, 2021

RAMAN: Reinforcement Learning Inspired Algorithm for Mapping Applications onto Mesh Network-on-Chip.

Jitesh Choudhary, Soumya J., Linga Reddy Cenkeramaddi

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications.

M. K. Aparna Nair, P. Veda Bhanu, Soumya J., Linga Reddy Cenkeramaddi

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Angle and Height Estimation Technique for Aerial Vehicles using mmWave FMCW Radar.

Prabhat Kumar Rai, Abhinav Kumar, Mohammed Zafar Ali Khan, Soumya J., Linga Reddy Cenkeramaddi

Proceedings of the 13th International Conference on COMmunication Systems & NETworkS, 2021

Object Classification Technique for mmWave FMCW Radars using Range-FFT Features.

Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh Kumar Vishvakarma, Soumya J., M. B. Srinivas, Phaneendra K. Yalavarthy, Abhinav Kumar, V. Lalitha, Sagar Koorapati, Linga Reddy Cenkeramaddi

Proceedings of the 13th International Conference on COMmunication Systems & NETworkS, 2021

2020

Fault-Tolerant Routing Algorithm for Mesh based NoC using Reinforcement Learning.

Jagadheesh Samala, Harshvardhan C. Takawale, Yash Chokhani, P. Veda Bhanu, Soumya J.

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A Self-Powered Long-range Wireless IoT Device based on LoRaWAN.

Hari Bhusal, Pankaj Khatiwada, Ajit Jha, Soumya J., Sagar Koorapati, Linga Reddy Cenkeramaddi

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design.

P. Veda Bhanu, Chetan Vudadha, Soumya J.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement.

P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J.

ACM J. Emerg. Technol. Comput. Syst., 2019

Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimisation.

P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J.

J. Exp. Theor. Artif. Intell., 2019

Long-range & Self-powered IoT Devices for Agriculture & Aquaponics Based on Multi-hop Topology.

Rolf Arne Kjellby, Linga Reddy Cenkeramaddi, Anders Frøytlog, Baltasar Beferull-Lozano, Soumya J., Meghana Bhange

Proceedings of the 5th IEEE World Forum on Internet of Things, 2019

Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture.

Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J., Linga Reddy Cenkeramaddi

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture.

P. Veda Bhanu, Pranav Venkatesh Kulkarni, Sai Pranavi Avadhanam, Soumya J., Linga Reddy Cenkeramaddi

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

FPGA Implementation of Novel Routing Algorithm for Butterfly-Fat-Tree Topology based NoC Design.

P. Veda Bhanu, S. Jagadheesh, Vasanth Bhat, Garima Agarwal, Soumya J.

Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

A Link Fault Tolerant Routing Algorithm for Mesh of Tree Based Network-on-Chips.

Joshua Pushparaj, P. Veda Bhanu, Soumya J.

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization.

P. Veda Bhanu, Soumya J.

Proceedings of the 14th Conference on Industrial and Information Systems, 2019

2018

A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips.

Monil Shah, Mohit Upadhyay, P. Veda Bhanu, Soumya J., Linga Reddy Cenkeramaddi

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design.

Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J., Linga Reddy Cenkeramaddi, Henning Idsoe

Proceedings of the TENCON 2018, 2018

Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization.

P. Veda Bhanu, Pranav Venkatesh Kulkarni, Sarthak Jain, Soumya J., Linga Reddy Cenkeramaddi, Henning Idsoe

Proceedings of the TENCON 2018, 2018

Dn-FTR: Fault-tolerant routing algorithm for Mesh based network-on-chip.

Divvya Sinha, Ashmita Roy, Kunchakuri Varun Kumar, Pranav Venkatesh Kulkarni, Soumya J.

Proceedings of the 2018 4th International Conference on Recent Advances in Information Technology (RAIT), 2018

Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement.

P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J., Linga Reddy Cenkeramaddi, Henning Idsoe

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

Sensor Data Compression Based on Re-Quantization of Sensor Data.

Henning Idsoe, Linga Reddy Cenkeramaddi, Soumya J.

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Design of Software and Data Analytics for Self-Powered Wireless IoT Devices.

Linga Reddy Cenkeramaddi, Ashish Goyal, Asheesh Bhuria, M. B. Srinivas, Soumya J.

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration.

Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J., Linga Reddy Cenkeramaddi

Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Self-powered IoT Device based on Energy Harvesting for Remote Applications.

Rolf Arne Kjellby, Linga Reddy Cenkeramaddi, Thor Eirik Johnsrud, Svein Erik Løtveit, Geir Jevne, Baltasar Beferull-Lozano, Soumya J.

Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2018

2017

Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture.

Soumya J., K. Niranjan Babu, Santanu Chattopadhyay

J. Circuits Syst. Comput., 2017

Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes.

Grandhi Sai Anirudh, Soumya J.

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Fault-tolerant application specific Network-on-Chip design.

Parth Shah, Kanniganti Abhishek, Soumya J.

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

2016

Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels.

Sandeep D'Souza, Soumya J., Santanu Chattopadhyay

ACM Trans. Archit. Code Optim., 2016

2015

Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores.

Soumya J., Srijan Tiwary, Santanu Chattopadhyay

J. Syst. Archit., 2015

Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes.

Soumya J., Kundan Kumar, Santanu Chattopadhyay

J. Syst. Archit., 2015

A constructive heuristic for application mapping onto an express channel based Network-on-Chip.

Sandeep D'Souza, Soumya J., Santanu Chattopadhyay

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration.

Soumya J., Ashish Sharma, Santanu Chattopadhyay

ACM Trans. Reconfigurable Technol. Syst., 2014

A locally reconfigurable Network-on-Chip architecture and application mapping onto it.

Soumya J., Ashish Sharma, Santanu Chattopadhyay

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2013

Application-Specific Network-on-Chip synthesis with flexible router Placement.

Soumya J., Santanu Chattopadhyay

J. Syst. Archit., 2013

2012

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router.

Santanu Kundu, Soumya J., Santanu Chattopadhyay

Microprocess. Microsystems, 2012

2011

Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis.

Soumya J., Putta Venkatesh, Santanu Chattopadhyay

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011